Abstract: Disclosed herein are azidodeoxy- and aminodeoxy trehalose (TreAz and TreNH2) compounds that inhibit Mycobacterium tuberculosis (an etiological agent of TB) biofilm (an in vitro model of intent TB infection) formation via blocking of the adaptive strategy used by M. tuberculosis form biofilm, termed trehalose catalytic shift. Prior to our work, such compounds were never tested for inhibition of mycobacterial biofilm formation. Our work defined this class of compounds' mechanism of action and showed for the first time that they sensitize drug-tolerant mycobacteria to existing clinically used antibiotics. The disclosed compounds are potential drugs for adjunctive treatment of TB and related mycobacterial diseases.

Abstract: Disclosed is a data processing device of the spiking neural network, which includes a discretizer that receives time-series data, discretizes the time-series data based on sampling, and outputs sampled time-series data, and a control unit that receives the sampled time-series data, extracts a voltage feature and a time feature from the sampled time-series data, and increases the number of spikes firing in an input neuron each corresponding to the voltage feature and the time feature extracted from a plurality of input neurons including first to n-th input neurons, with respect to the “n”, which is an arbitrary positive integer.

Abstract: An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.

Abstract: A pumping voltage generating circuit can include a control information generating block receiving a pumping enable signal and a refresh sequential signal and generating driving force control information, the driving force control information controlled so that a number of pulses of the refresh sequential signal falling within a target pulse number range is generated during the generation of pulses of the pumping enable signal which have the pumping reference number, a pumping generation block generating a pumping voltage with a total pumping force, the total pumping force depending on the data value of the driving force control information, and a level detection block detecting a level of the pumping voltage and generating the pumping enable signal, the pumping enable signal activated when the level of the pumping voltage is outside a target level range, and deactivated when the level of the pumping voltage falls within the target level range.

Abstract: An image data obtainment device includes a camera module, a pattern mount part, and a housing in which the camera module is positioned. The camera module generates image data for image restoration training. The pattern mount part may selectively position a dummy pattern on the camera module. The pattern mount part is positioned on the housing.

Abstract: An image data pair for image restoration training is generated by an image preprocessing method. The image preprocessing method includes receiving first image data and second image data, generating reference image data based on the first image data, generating a plurality of crop image data based on the second image data, selecting crop image data based on a smallest loss function value among loss function values generated based on each of the reference image data and the plurality of crop image data, and outputting the reference image data and the selected crop image data as the image data pair.

Abstract: The present disclosure relates to a substrate monitoring method and a substrate processing apparatus, and more particularly, to a substrate monitoring method and a substrate processing apparatus for detecting a warpage degree of a substrate by measuring a capacitance between an upper electrode and the substrate in a chamber when various processes are performed on the substrate.

Abstract: A bit line pre-charge voltage generating circuit in a semiconductor memory device may reduce current consumption. The bit line pre-charge voltage generating circuit includes a reference voltage generating portion that generates a pull-down reference voltage and a pull-up reference voltage; a comparing portion that generates a pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage, and generates a pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage; a driving portion that includes a pull-up driving element and a pull-down driving element; and an activation overlap reduction portion that generates the pull-up control signal and the pull-down control signal The activation overlap reduction portion can minimize the overlap between the turn-on sections of the pull-up driving element and the pull-down driving element of the driving portion.

Abstract: A light emitting element layer of a display device is disposed on a base layer. A first light emitting part of the light emitting element layer includes first organic patterns emitting light, a charge generation layer is disposed on the first light emitting part, and a second light emitting part is disposed on the charge generation layer. The second light emitting part covers the charge generation layer in a plan view. The second light emitting part includes second organic patterns disposed in a display area and emitting light and dummy patterns disposed in a non-display area.

Abstract: Provided is a communication method by which a transmitting device and a receiving device communicate through a request channel and a reply channel, the communication method including: outputting, by the transmitting device, a burden signal including data to the receiving device through the request channel; storing, by the receiving device, the data; providing, by the transmitting signal, a reply request signal indicating whether a reply is required; and performing, by the receiving device, a reply to the stored data through the reply channel according to the reply request signal.

Abstract: Provided is a system for time synchronization between a server and an Internet-of-Things (IoT) device. The system may include a server configured to broadcast a time-point synchronization signal including absolute time point information; and an IoT device configured to receive the broadcast time-point synchronization signal and calculate absolute time point information by using the absolute time point information included in the time-point synchronization signal, computation time information according to an internal computation operation, and transmission time information required to receive the time-point synchronization signal.

Abstract: Disclosed is a network-on-chip including a first data converter that receives first image data and second image data from at least one image sensor and encodes one image data among the first image data and the second image data, into first data, based on whether the first image data is identical to the second image data and a second data converter that receives non-image data from at least one non-image sensor and encodes the received non-image data into second data. The network-on-chip outputs the first data and the second data to transmit the first data and the second data to an external server at a burst length.

Abstract: A data transmission/reception device comprises a data bus; a data transmission circuit that recognizes standard data, receives a transmission data, loads a code data into the data bus, and generates a flag signal; and a data reception circuit that receives the flag signal and the code data transmitted through the data bus, and recovers the code data into a reception data according to the activation of the flag signal. According to the data transmission/reception device of the disclosure, current consumption may be reduced during data transmission.

Abstract: A signal input buffer includes 1-st and 2-nd buffering blocks; a 1-st input switching block; a 2-nd input switching block; a 1-st output switching block; and a 2-nd output switching block. The signal input buffer buffers a reception signal pair and generates a buffered signal pair, and is capable of operation in a normal mode and a calibration mode, the reception signal pair includes an intrinsic reception signal and a complementary reception signal, the buffered signal pair includes an intrinsic buffered signal and a complementary buffered signal, and the calibration mode includes a 1-st calibration period and a 2-nd calibration period.

Abstract: Disclosed is a wake-up circuit including a preprocessing unit that generates a first signal by removing noise from an input signal, a comparison unit that generates a second signal based on the first signal and weight data, an output circuit that generates a power signal based on the second signal and an initialization signal, and a micro control unit (MCU) that generates the initialization signal based on a state signal received from the output circuit. The comparison unit includes a spike neuron network structure that generates the second signal by applying the weight data to the first signal. The output circuit supplies power to an external sensor node in response to the power signal.

Abstract: Disclosed is an operating method of a user communication device, which includes receiving a wakeup signal from a stationary communication device over a first human body communication channel, the wakeup signal having a frequency in a low frequency band, switching from a standby mode to a wakeup mode in response to the wakeup signal, and receiving a data signal from the stationary communication device over the first human body communication channel during the wakeup mode, and the first human body communication channel is provided by a body of a user of the user communication device.

Abstract: Disclosed herein is an apparatus and method for controlling nonvolatile memory. The apparatus may include nonvolatile memory and a memory controller for issuing a serial clock (SCK) to the nonvolatile memory and transferring data corresponding to a requested command to the nonvolatile memory or receiving data corresponding to a requested command from the nonvolatile memory and outputting the data to the outside through a serial-in or a serial-out in response to a read request or a write request.

Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates first and second input spike signals, a synapse circuit that generates a first current based on the first input spike signal and a weight and generates a second current based on the second input spike signal and the weight, a capacitor that forms a first membrane voltage based on the first current, and a neuron circuit including a comparator and that resets the first membrane voltage, and after the capacitor further forms a second membrane voltage based on the second current, and the comparator includes a first input terminal and a second input terminal, receives the first membrane voltage through the first input terminal and a reference voltage through the second input terminal, generates a first spike signal based on a first comparison operation of the first membrane voltage and the reference voltage.

Abstract: An analog-to-digital converter may comprise a code voltage generating part that generates a conversion code voltage according to the conversion digital code; a voltage comparing part that generates a comparison result signal by comparing the input analog voltage and the conversion code voltage; a shifting register that receives a clock signal and generates a 1-st to a n-th control pulse signals; and a code generating part that generates the conversion digital code with receiving by comparison result signal and the 1-st to the n-th control pulse signals.

Abstract: An input buffer circuit includes a reception sensing part that receives an input signal pair to generate an intermediate signal pair, a comparison buffering part that buffers the intermediate signal pair to generate a buffered signal pair, an intrinsic buffered signal of the buffered signal pair being controlled to a first logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, a complementary buffered signal of the buffered signal pair is controlled to a second logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, and a hysteresis control part that drives the buffered signal pair to have forward hysteresis by using at least one of the intrinsic buffered signal and the complementary buffered signal.