Abstract: A bit line pre-charge voltage generating circuit in a semiconductor memory device may reduce current consumption. The bit line pre-charge voltage generating circuit includes a reference voltage generating portion that generates a pull-down reference voltage and a pull-up reference voltage; a comparing portion that generates a pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage, and generates a pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage; a driving portion that includes a pull-up driving element and a pull-down driving element; and an activation overlap reduction portion that generates the pull-up control signal and the pull-down control signal The activation overlap reduction portion can minimize the overlap between the turn-on sections of the pull-up driving element and the pull-down driving element of the driving portion.

Abstract: In one example, an electronic device includes a first substrate, an electronic component coupled to a side of the first substrate, and a vertical interconnect structure coupled to the side of the first substrate. The vertical interconnect structure includes a first interconnect structure coupled to the side of the first substrate, and an intermediate substrate having a first side coupled to the first interconnect structure. The intermediate substrate comprises inner sidewalls defining a cavity with the electronic component extending through the cavity. A second interconnect structure can be coupled to a second side of the intermediate substrate opposite the first side of the intermediate substrate. An encapsulant can be disposed over the first substrate and the intermediate substrate, around the electronic component, around the first interconnect structure, around the second interconnect structure, and around the intermediate substrate. Other examples and related methods are also disclosed herein.

Abstract: In one example, an electronic device includes a first substrate, an electronic component disposed over a side of the first substrate, and a vertical interconnect structure coupled to the side of the first substrate. The vertical interconnect structure comprises a first metallic core structure coupled to the side of the first substrate, a second metallic core structure coupled to the first metallic core structure, and a fusible material coupling the first metallic core structure with the second metallic core structure. The fusible material also couples the first metallic core structure to the first substrate. A second substrate can be disposed over the electronic component and the vertical interconnect structure. The second metallic core structure of the vertical interconnect structure can be coupled to the second substrate by the fusible material. An encapsulant can be disposed over the electronic component. Other examples and related methods are also disclosed herein.

Abstract: In one example, an electronic device includes a first substrate and an electronic component coupled to an inner side of the first substrate. A vertical interconnect structure can be coupled to the inner side of the first substrate and may include a core structure coupled to the first substrate, a wire coupled to the core structure and opposite the first substrate, and an encapsulant disposed around the wire. The device also includes a second substrate disposed over the electronic component and coupled to the vertical interconnect structure. The encapsulant can comprise protrusions and a recessed side that define a cavity. The wire can protrude from the encapsulant into the cavity.

Abstract: In one example, an electronic device comprises a substrate having a first conductive structure, an electronic component coupled to the first conductive structure at a first side of the substrate, wherein the electronic component includes a first side facing the first side of the substrate and a second side opposite the first side, vertical interconnects around the electronic component, wherein the vertical interconnects are coupled to the first conductive structure at the first side of the substrate, an interposer having a second conductive structure coupled to the plurality of vertical interconnects, a thermal body coupled between the electronic component and the interposer, and an encapsulant between the substrate and the interposer, around the thermal body, around the plurality of vertical interconnects, and around the electronic component. Other examples and related methods are also disclosed herein.

Abstract: A storage system for simulating a quantum circuit includes multiple storage devices, wherein the multiple storage devices may be connected to a host device through a redundant array of independent disks (RAID) expansion card and may read data consecutively stored in a first storage device among the multiple storage devices to a main memory with a single access to the first storage device in response to a data read request for an operation in the main memory of the host device.

Abstract: A data input buffer includes a switching circuit; a reception circuit that includes a reception response unit and a reference response unit; and a code generating circuit. The data input buffer buffers a reception data signal to generate a buffered data signal, the reception data signal being an analog signal, and the buffered data signal being a digital signal, and a relative magnitude of a reference response conductance with respect to the reception response conductance is sequentially changed according to a sequential change of the calibration code, in the calibration mode.

Abstract: The present invention relates to a hybrid neural network apparatus. The hybrid neural network apparatus includes an input layer group comprising at least one analog neural network (ANN) layer and trained by information or data input from an application system, an intermediate layer group comprising at least one spiking neural network (SNN) layer and trained by a received training result of the input layer group, and an output layer group comprising at least one ANN layer, trained by a received training result of the intermediate layer group, and then outputting a final training result to the application system.

Abstract: A quantum circuit simulation device according to the present disclosure includes a storage system including one or more storage devices, and a host system connected to the storage system and configured to simulate a quantum circuit, wherein the quantum circuit stored in the storage system may be partitioned into one or more sub-circuits, and the host system may sequentially simulate the one or more sub-circuits in a main memory.

Abstract: A semiconductor memory device of the disclosure comprises a frequency detection circuit that detects the frequency of an input clock signal generated during a measurement time and generates a frequency confirmation data having the information on the frequency of the input clock signal; a status register that receives the frequency confirmation data and generates 1-st to m-th driving control signals; and a 1-st to an m-th operating circuit. In the semiconductor memory device of the disclosure, the operating state can be changed by detecting a frequency change of an input clock signal without an external mode register setting command. As a result, according to the semiconductor memory device of the disclosure, the time required to change the operating mode is reduced.

Abstract: Disclosed herein are azidodeoxy- and aminodeoxy trehalose (TreAz and TreNH2) compounds that inhibit Mycobacterium tuberculosis (an etiological agent of TB) biofilm (an in vitro model of intent TB infection) formation via blocking of the adaptive strategy used by M. tuberculosis form biofilm, termed trehalose catalytic shift. Prior to our work, such compounds were never tested for inhibition of mycobacterial biofilm formation. Our work defined this class of compounds' mechanism of action and showed for the first time that they sensitize drug-tolerant mycobacteria to existing clinically used antibiotics. The disclosed compounds are potential drugs for adjunctive treatment of TB and related mycobacterial diseases.

Abstract: An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.

Abstract: A pumping voltage generating circuit can include a control information generating block receiving a pumping enable signal and a refresh sequential signal and generating driving force control information, the driving force control information controlled so that a number of pulses of the refresh sequential signal falling within a target pulse number range is generated during the generation of pulses of the pumping enable signal which have the pumping reference number, a pumping generation block generating a pumping voltage with a total pumping force, the total pumping force depending on the data value of the driving force control information, and a level detection block detecting a level of the pumping voltage and generating the pumping enable signal, the pumping enable signal activated when the level of the pumping voltage is outside a target level range, and deactivated when the level of the pumping voltage falls within the target level range.

Abstract: A method and a device for recognizing an object are disclosed. The object recognizing device includes an electrode array including a plurality of drive electrodes and a plurality of sense electrodes; a sensing circuit configured to generate a pulse train representing spatial information and material information on an object positioned over the electrode array based on mutual capacitances formed between the plurality of drive electrodes and the plurality of sense electrodes; and a neuron network processor configured to recognize the object positioned over the electrode array based on the pulse train.

Abstract: An image data obtainment device includes a camera module, a pattern mount part, and a housing in which the camera module is positioned. The camera module generates image data for image restoration training. The pattern mount part may selectively position a dummy pattern on the camera module. The pattern mount part is positioned on the housing.

Abstract: An image data pair for image restoration training is generated by an image preprocessing method. The image preprocessing method includes receiving first image data and second image data, generating reference image data based on the first image data, generating a plurality of crop image data based on the second image data, selecting crop image data based on a smallest loss function value among loss function values generated based on each of the reference image data and the plurality of crop image data, and outputting the reference image data and the selected crop image data as the image data pair.

Abstract: A bit line pre-charge voltage generating circuit in a semiconductor memory device may reduce current consumption. The bit line pre-charge voltage generating circuit includes a reference voltage generating portion that generates a pull-down reference voltage and a pull-up reference voltage; a comparing portion that generates a pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage, and generates a pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage; a driving portion that includes a pull-up driving element and a pull-down driving element; and an activation overlap reduction portion that generates the pull-up control signal and the pull-down control signal The activation overlap reduction portion can minimize the overlap between the turn-on sections of the pull-up driving element and the pull-down driving element of the driving portion.

Abstract: A light emitting element layer of a display device is disposed on a base layer. A first light emitting part of the light emitting element layer includes first organic patterns emitting light, a charge generation layer is disposed on the first light emitting part, and a second light emitting part is disposed on the charge generation layer. The second light emitting part covers the charge generation layer in a plan view. The second light emitting part includes second organic patterns disposed in a display area and emitting light and dummy patterns disposed in a non-display area.

Abstract: Provided is a system for time synchronization between a server and an Internet-of-Things (IoT) device. The system may include a server configured to broadcast a time-point synchronization signal including absolute time point information; and an IoT device configured to receive the broadcast time-point synchronization signal and calculate absolute time point information by using the absolute time point information included in the time-point synchronization signal, computation time information according to an internal computation operation, and transmission time information required to receive the time-point synchronization signal.

Abstract: A data transmission/reception device comprises a data bus; a data transmission circuit that recognizes standard data, receives a transmission data, loads a code data into the data bus, and generates a flag signal; and a data reception circuit that receives the flag signal and the code data transmitted through the data bus, and recovers the code data into a reception data according to the activation of the flag signal. According to the data transmission/reception device of the disclosure, current consumption may be reduced during data transmission.