Abstract: Provided are a method for generating a summary and a system therefor. The method according to some embodiments may include calculating a likelihood loss for a summary model using a first text sample and a first summary sentence corresponding to the first text sample, calculating an unlikelihood loss for the summary model using a second text sample and the first summary sentence, the second text sample being a negative sample generated from the first text sample, and updating the summary model based on the likelihood loss and the unlikelihood loss.

Abstract: The present disclosure provides a waveguide display apparatus. The waveguide waveguide display apparatus of the present disclosure is a waveguide display apparatus for correcting curved surface reflection distortion, the waveguide display apparatus including a waveguide for guiding light inputted from the outside; a first diffractive optical element disposed at the waveguide, and diffracting the light inputted from the outside to the inside of the waveguide; and a second diffractive optical element disposed at the waveguide, and diffracting the light guided by the waveguide to output a plurality of diffracted lights in a direction of a curved surface reflector located outside, wherein the second diffractive optical element has a structure of a diffraction grating corresponding to a curvature of the curved surface reflector such that the diffracted lights are reflected at different locations of the curved surface reflector in directions parallel to each other.

Abstract: An inverter circuit in a scan driving circuit of a display device that includes an output transistor connected between a first voltage line and an output terminal outputting a second start signal and including a gate electrode connected to an input terminal receiving a first start signal, a first switching transistor connected between the first voltage line and the output terminal and including a gate electrode connected to a first switching line receiving a first switching signal, a second switching transistor connected between the output terminal and a first node and including a gate electrode connected to a second switching line receiving a second switching signal, and a discharge circuit that discharges the first node to a first bias clock signal in response to the first start signal, the first bias clock signal, and a second bias clock signal.

Abstract: A pixel circuit includes a light emitting element, a first transistor, a second transistor, and a third transistor. The first transistor applies a driving current to the light emitting element. The second transistor and the third transistor apply an initialization voltage to a first electrode of the light emitting element. The second transistor and the third transistor are electrically connected to each other in series.

Abstract: A picture generation apparatus and a control method thereof are disclosed. An embodiment of the present disclosure provides a picture generation apparatus including a light source; a Spatial Light Modulator (SLM) configured to output an image using light transmitted from the light source; and a control unit configured to control the light source and the SLM based on at least one of illuminance of the surroundings or content of the image.

Abstract: A scan driver for driving a plurality of pixels, the scan driver including: stages connected to each other through carry lines, a first stage among the stages includes: a first scan circuit configured to generate a first scan signal in response to a stage select signal, and apply the first scan signal to pixels of the same row among the plurality of pixels; and a second scan circuit electrically connected to the first scan circuit to generate a carry signal overlapping the first scan signal, and configured to provide a second scan signal to the pixels of the same row in response to the carry signal, and the carry signal is output as the stage select signal to a second stage among the stages through one of the carry lines.

Abstract: Provided is a gate driver comprising an inverter inverting a start signal to generate an inverted start signal, a first driver including a first stage generating a bias gate signal to initialize a light emitting element of each of pixels in response to the inverted start signal, and a second driver including a second stage generating a write gate signal to apply data voltages to the pixels in response to the start signal. Accordingly, the gate driver may generate a plurality of gate signals using one start signal. In addition, since the gate driver generates a write gate signal and a bias gate signal using one start signal, a bias operation and a light emitting element initialization operation may be performed in a self-scan period without adding the start signal. Further, a size of the gate driver may be reduced, and accordingly, the gate driver may be efficiently disposed.

Abstract: A repair pixel and a display apparatus including the repair pixel, the display panel including a repair pixel for a pixel row or a plurality of repair pixels for a pixel row so that repair may be performed using the repair pixel when a bad pixel occurs in the corresponding pixel row. The bad pixel is repaired using the repair pixel so that the yield of the display panel may be enhanced.

Abstract: A pixel circuit includes a light emitting element, a first transistor, a second transistor, and a third transistor. The first transistor applies a driving current to the light emitting element. The second transistor and the third transistor apply an initialization voltage to a first electrode of the light emitting element. The second transistor and the third transistor are electrically connected to each other in series.

Abstract: Disclosed herein are a display device, and a method of testing a display device. The display device includes sub-pixels arranged along pixel columns, wire pads disposed in a non-display area and disposed on one side of the display area, fan-out lines extending in a first direction and connecting the sub-pixels with the wire pads, data lines extending in the first direction and connected to the fan-out lines, connection wires connecting the fan-out lines with the data lines, at least one of the connection wires including a first portion passing through the display area and extending in a second direction crossing the first direction; and a test unit disposed between the wire pads and the display area and electrically connected to the fan-out lines. The test unit applies a test voltage to the fan-out lines to check a short-circuit or an open-circuit in the fan-out lines.

Abstract: A method of inspecting a display panel includes testing a pixel circuit including a plurality of transistors and a capacitor in the display panel. The testing of the pixel circuit includes: providing a first test voltage to a first node to which a first electrode of the capacitor is connected, providing a second test voltage different from the first test voltage to a second node to which a second electrode of the capacitor is connected, and detecting a defect in the pixel circuit through a test transistor connected to the first node among the plurality of transistors.

Abstract: The present invention relates to the preparation of mesenchymal stem cells, which are for the proliferation of viral vectors and viruses, and enable virus production and release timing control such that tumor targeting can be improved and viruses can be mass-produced. In addition, the tumorigenesis of mesenchymal stem cells of the present invention can be fundamentally blocked, safety is secured by enabling virus production and release to be controlled at desired time points, and antitumor effects can be maximized.

Abstract: A repair pixel and a display apparatus including the repair pixel, the display panel including a repair pixel for a pixel row or a plurality of repair pixels for a pixel row so that repair may be performed using the repair pixel when a bad pixel occurs in the corresponding pixel row. The bad pixel is repaired using the repair pixel so that the yield of the display panel may be enhanced.

Abstract: A gate driver including a plurality of stages, each of the plurality of stages including an eighth transistor connected between a third power input terminal and an output terminal, the eighth transistor including a gate electrode connected to a fourth node, a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node, an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node, a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal, and a third capacitor connected between the third power input terminal and the fourth node.

Abstract: Disclosed herein is an amyloid ? accumulation and/or aggregation inhibitor. A technique for inhibiting amyloid ? accumulation and/or aggregation by concurrently introducing Nurr1 and Foxa2 genes and introducing the co-expression of the genes is also provided. When used, the composition can be applied to the prevention or treatment of a neurodegenerative disease caused by amyloid ? accumulation and/or aggregation, such as Alzheimer's disease.

Abstract: A display device includes: a substrate including a display area and a non-display area; pixels connected to first scan lines, second scan lines, third scan lines, and emission control lines; a first scan driver supplying a first scan signal to the first scan lines; a second scan driver supplying a second scan signal to some of the second scan lines and supplying a third scan signal to the third scan lines; an emission driver supplying an emission control signal to the emission control lines; a first pad and a second pad provided in the non-display area; a first power line connected to the first pad, the first power line transferring a first voltage to the first scan driver and the emission driver; and a second power line connected to the second pad, the second power line transferring a second voltage to the second scan driver.

Abstract: A display device includes: a substrate including a display area and a non-display area; pixels connected to first scan lines, second scan lines, third scan lines, and emission control lines; a first scan driver supplying a first scan signal to the first scan lines; a second scan driver supplying a second scan signal to some of the second scan lines and supplying a third scan signal to the third scan lines; an emission driver supplying an emission control signal to the emission control lines; a first pad and a second pad provided in the non-display area; a first power line connected to the first pad, the first power line transferring a first voltage to the first scan driver and the emission driver; and a second power line connected to the second pad, the second power line transferring a second voltage to the second scan driver.

Abstract: The present invention relates to an anti-tumor composition which includes a GM-CSF gene; an Flt3L-TRAIL fusion gene; shRNA inhibiting TGF-? expression; and shRNA inhibiting HSP expression.

Abstract: Disclosed herein is an amyloid ? accumulation and/or aggregation inhibitor. A technique for inhibiting amyloid ? accumulation and/or aggregation by concurrently introducing Nurr1 and Foxa2 genes and introducing the co-expression of the genes is also provided. When used, the composition can be applied to the prevention or treatment of a neurodegenerative disease caused by amyloid ? accumulation and/or aggregation, such as Alzheimer's disease.

Abstract: A display device includes: a display panel in which a plurality of pixels are arranged; a plurality of gate lines disposed in the display panel and transmitting a gate signal to the plurality of pixels; a gate driver disposed in the display panel and including a plurality of stages for generating the gate signal and outputting the gate signal to the plurality of gate lines; and a plurality of clock signal lines disposed in the display panel and transmitting a clock signal to the plurality of stages. Each stage of the plurality of stages includes a clock signal terminal connected to one of the plurality of clock signal lines to receive the clock signal, a first output terminal connected to a corresponding gate line to output the gate signal, and a first transistor and a second transistor connected to the first output terminal.