Patents by Inventor Jaejoo Cho

Jaejoo Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for connecting flip chip components
    Patent number: 8601429
    Abstract: An automated system and method for determining flip chip connections involves generating a first projection that includes representations of bumps arranged over a core of the flip chip and generating a second projection that includes representations of I/O pads arranged around the core. The first projection is generated by drawing a line through each bump between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the bump. The outer portion of the flip chip is traversed, and the first projection is generated based on the order in which bump representations are encountered. The second projection is generated by drawing a line through each I/O pad between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the I/O pad.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: December 3, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tao Yao, Phil Tu, Jaejoo Cho
  • Method for connecting flip chip components
    Patent number: 7871831
    Abstract: An automated system and method for determining flip chip connections involves generating a first projection that includes representations of bumps arranged over a core of the flip chip and generating a second projection that includes representations of I/O pads arranged around the core. The first projection is generated by drawing a line through each bump between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the bump. The outer portion of the flip chip is traversed, and the first projection is generated based on the order in which bump representations are encountered. The second projection is generated by drawing a line through each I/O pad between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the I/O pad.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: January 18, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tao Yao, Phil Tu, Jaejoo Cho