Abstract: A decoupling capacitor includes a first insulating layer extending in a horizontal direction, a storage plate arranged on the first insulating layer, a top plate facing the storage plate, a second insulating layer interposed between the storage plate and the top plate and having a plurality of through holes, a capacitor block including a plurality of capacitor structures in the plurality of through holes, a wiring structure covering the top plate, a first conductive pad arranged on the wiring structure and configured to be electrically connected to the storage plate through a first conductive path of the wiring structure, and a second conductive pad spaced apart from the first conductive pad in the horizontal direction in the same plane as the first conductive pad and configured to be electrically connected to the top plate through a second conductive path of the wiring structure.

Abstract: A decoupling capacitor includes a first insulating layer extending in a horizontal direction, a storage plate arranged on the first insulating layer, a top plate facing the storage plate, a second insulating layer interposed between the storage plate and the top plate and having a plurality of through holes, a capacitor block including a plurality of capacitor structures in the plurality of through holes, a wiring structure covering the top plate, a first conductive pad arranged on the wiring structure and configured to be electrically connected to the storage plate through a first conductive path of the wiring structure, and a second conductive pad spaced apart from the first conductive pad in the horizontal direction in the same plane as the first conductive pad and configured to be electrically connected to the top plate through a second conductive path of the wiring structure.

Abstract: A capacitive sensor including a substrate, a semiconductor chip on the substrate, at least one bonding wire electrically connecting a top surface of the semiconductor chip to a top surface of the substrate, and a plurality of sensor electrodes on the top surface of the semiconductor chip may be provided. In particular, heights of the sensor electrodes may be provided to be greater than a height of the at least one bonding wire with respect to the top surface of the semiconductor chip.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, an epitaxial layer having a second conductivity type, an isolation area in the epitaxial layer to define an active area of the semiconductor substrate, a body area having a first conductivity type and a drift area having a second conductivity type adjacent to each other in the epitaxial layer, a LOCOS insulating layer in the drift area and surrounded by the drift area, a drain area adjacent to a side part of the LOCOS insulating layer and surrounded by the drift area, a body contact area and a source area in the body area and surrounded by the body area, and a gate area overlapping the drift area and a part of the LOCOS insulating layer from a direction of the body area.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, an epitaxial layer having a second conductivity type, an isolation area in the epitaxial layer to define an active area of the semiconductor substrate, a body area having a first conductivity type and a drift area having a second conductivity type adjacent to each other in the epitaxial layer, a LOCOS insulating layer in the drift area and surrounded by the drift area, a drain area adjacent to a side part of the LOCOS insulating layer and surrounded by the drift area, a body contact area and a source area in the body area and surrounded by the body area, and a gate area overlapping the drift area and a part of the LOCOS insulating layer from a direction of the body area.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a mesh-type gate electrode including first portions extending in a first direction and second portions extending in a second direction crossing the first direction over the substrate. The mesh-type gate structure may have a plurality of openings, and source regions and drain regions of second conductivity type alternately arranged in the first direction and the second direction in the substrate at locations corresponding to the openings.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a mesh-type gate electrode including first portions extending in a first direction and second portions extending in a second direction crossing the first direction over the substrate. The mesh-type gate structure may have a plurality of openings, and source regions and drain regions of second conductivity type alternately arranged in the first direction and the second direction in the substrate at locations corresponding to the openings.

Abstract: A diode, includes a semiconductor substrate, a first region doped with a first dopant type in the substrate, a second region doped with a second dopant type in the substrate, a first well of the first dopant type in the substrate and surrounding the first region and the second region, and a second well of the second dopant type in the substrate connecting the first region and the second region. The first dopant type is opposite the second dopant type.

Abstract: Non-volatile (NV) semiconductor memories and methods of operating the same to reduce or eliminate a need for an external capacitance are provided. In one embodiment, the memory includes a memory cell comprising a random access memory (RAM) portion and a NV memory portion, and the method comprises steps of: (i) initially erasing the NV memory portion; and (ii) on detecting a drop in power supplied to the memory, programming the NV memory portion with data from the RAM portion while powering the memory from a capacitor. On restoration of power data is recalled from the NV memory portion into the RAM portion, and the NV memory portion erased. Preferably, the capacitor is integrally formed on a single substrate with the NV memory portion and RAM portion. More preferably, the capacitor comprises intrinsic capacitance between elements of the memory formed on the substrate. Other embodiments are also disclosed.