Patents by Inventor Jae-Kyung Yoo

Jae-Kyung Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240159653
    Abstract: A method for evaluating an adhesive strength of a separator including manufacturing an electrode-separator composite including an electrode stacked on at least one surface of a separator, and the at least one surface of the separator and a surface of the electrode facing the at least one surface include adhesive surfaces and non-adhesive surfaces, and the adhesive surfaces and the non-adhesive surfaces are alternately disposed; moving the electrode-separator composite; cutting the electrode-separator composite in a direction parallel to the moving direction; attaching measuring rolls respectively to both surfaces of the cut electrode-separator composite; separating the electrode-separator composite by rotating each of the attached measuring rolls and spacing the measuring rolls apart from each other; and measuring a torque generated by the measuring rolls while separating the electrode-separator composite.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 16, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Hyun Kyung SHIN, Jae Woong YOO
  • Publication number: 20240092913
    Abstract: The present disclosure relates to an isolated anti-FcRN antibody, which is an antibody binding to FcRN (stands for neonatal Fc receptor, also called FcRP, FcRB or Brambell receptor) that is a receptor with a high affinity for IgG or a fragment thereof, a method of preparing thereof, a composition for treating autoimmune disease, which comprises the antibody, and a method of treating and diagnosing autoimmunre diseases using the antibody. The FcRn-specific antibody according to the present disclosure binds to FcRn non-competitively with IgG to reduce serum pathogenic auto-antibody levels, and thus can be used for the treatment of autoimmune diseases.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 21, 2024
    Applicant: HANALL BIOPHARMA CO., LTD.
    Inventors: Sung Wuk KIM, Seung Kook PARK, Jae Kap JEONG, Hyea Kyung AHN, Min Sun KIM, Eun Sun KIM, Hae-Young YONG, Dongok SHIN, Yeon Jung SONG, Tae Hyoung YOO
  • Patent number: 10867857
    Abstract: A method of cutting a substrate including a device region and a scribe lane region includes selectively forming a passivation layer in the device region of the substrate, selectively forming a self-assembled monolayer on the passivation layer, and performing plasma cutting in the scribe lane region.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Seong Jeon, Seung-Hun Shin, Jae-Kyung Yoo, Teak-Hoon Lee
  • Publication number: 20200273807
    Abstract: A semiconductor package includes a substrate having a silicon crystal structure, and at least one semiconductor chip provided on the substrate and having an upper surface, a lower surface, and a plurality of side surfaces, wherein the plurality of side surfaces are different from cleavage planes of the substrate.
    Type: Application
    Filed: July 17, 2019
    Publication date: August 27, 2020
    Inventors: Dong Hoon WON, Jae Kyung YOO
  • Publication number: 20200098635
    Abstract: A method of cutting a substrate including a device region and a scribe lane region includes selectively forming a passivation layer in the device region of the substrate, selectively forming a self-assembled monolayer on the passivation layer, and performing plasma cutting in the scribe lane region.
    Type: Application
    Filed: August 13, 2019
    Publication date: March 26, 2020
    Inventors: CHANG-SEONG JEON, SEUNG-HUN SHIN, JAE-KYUNG YOO, TEAK-HOON LEE
  • Patent number: 10510724
    Abstract: A semiconductor device package includes a buffer layer having an upper surface perpendicular to a first direction, a plurality of semiconductor chips stacked on the buffer layer one by one in the first direction, and a chip sealing material surrounding sidewalls of the semiconductor chips. The semiconductor chips include an upper semiconductor chip at a farthest position from the buffer layer and a remaining plurality of intermediate semiconductor chips. Each of the intermediate semiconductor chips includes through silicon vias (TSVs) passing through each of the intermediate semiconductor chips. The upper semiconductor chip includes a trench formed in at least a portion of a periphery of the upper semiconductor chip and covered by the chip sealing material. Accordingly, the semiconductor device package provides increased device reliability.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-kyung Yoo, Jin-woo Park
  • Publication number: 20190043831
    Abstract: A semiconductor device package includes a buffer layer having an upper surface perpendicular to a first direction, a plurality of semiconductor chips stacked on the buffer layer one by one in the first direction, and a chip sealing material surrounding sidewalls of the semiconductor chips. The semiconductor chips include an upper semiconductor chip at a farthest position from the buffer layer and a remaining plurality of intermediate semiconductor chips. Each of the intermediate semiconductor chips includes through silicon vias (TSVs) passing through each of the intermediate semiconductor chips. The upper semiconductor chip includes a trench formed in at least a portion of a periphery of the upper semiconductor chip and covered by the chip sealing material. Accordingly, the semiconductor device package provides increased device reliability.
    Type: Application
    Filed: December 5, 2017
    Publication date: February 7, 2019
    Inventors: Jae-kyung Yoo, Jin-woo Park
  • Publication number: 20090065128
    Abstract: A method for manufacturing a back seat for a solar cell module is disclosed, which method comprises a first step for unwinding a PET film wound on a roller; a second step for applying an adhesive on one surface of the unwound PET film; a third step for passing an adhesive applied PET film through a plurality of heating chambers which are sequentially arranged with different temperatures; a fourth step for cooling the PET film which is processed in the third step; a fifth step for unwinding the wound tedlar film and pressurizing and laminating the unwound tedlar film on an adhesive applied surface of the PET film cooled in the fourth step by a pressurizing roller; and a sixth step for winding the tedlar film-attached PET film on the roller.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 12, 2009
    Inventors: Jae-Hak Yoo, Jae-Kyung Yoo