Abstract: It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions comprise instructions to control each processor core of a plurality of processor cores of a first processing circuitry to execute a respective workload. The machine-readable instructions further comprise instructions to obtain temperature measurement data from each processor core of the plurality of processor cores. The temperature measurement data is acquired during the executing the respective workloads by the respective processor core of plurality of processor cores. The machine-readable instructions further comprise instructions to determine a physical layout of the first processing circuitry based on the obtained temperature measurement data from each processor core of the plurality of processor cores of the first processing circuitry.

Abstract: Some aspects of the present disclosure relate to an apparatus comprising memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores and to determine a first processor core of the plurality of processor cores to execute a first work-load based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

Abstract: A processing device (30, 710) for reducing scan traffic is provided. The processing device (30, 710) comprises one or more interfaces (32, 718) configured to transmit information to at least one register access interface (759, 761) and processing circuitry (34) configured to control the one or more interfaces. Further, the processing circuitry (34) is configured to obtain register parameters of at least one functional unit (760, 762) of a processing unit (750) and to generate an improved bulk register comprising the register parameters of the at least one functional unit.

Abstract: A memory system includes a memory device having a memory array that stores data based on address bits, including a row address. The memory system includes a memory controller having scrambler circuitry to apply a data mask to scramble data to be stored in the memory array. The scrambler can apply the data mask to scramble data for a write operation. The data scrambler can unscramble data for a read operation. The data mask has a pseudorandom pattern based at least in part on the row address of the data to be written or read.

Abstract: In some embodiments a method includes storing a micro-code patch stub in a micro-code patch memory, storing a micro-code patch corresponding to the micro-code patch stub in a system memory, in response to an event and in response to the stored micro-code patch stub, loading the stored micro-code patch from the system memory to the micro-code patch memory, and processing the micro-code patch from the micro-code patch memory. Other embodiments are described and claimed.

Abstract: In some embodiments a method includes storing a micro-code patch stub in a micro-code patch memory, storing a micro-code patch corresponding to the micro-code patch stub in a system memory, in response to an event and in response to the stored micro-code patch stub, loading the stored micro-code patch from the system memory to the micro-code patch memory, and processing the micro-code patch from the micro-code patch memory. Other embodiments are described and claimed.

Abstract: According to some embodiments, first data including a token is shifted into an IEEE 1149.1-compliant shift register and second data is received, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of the shifting of the first data. Next, it is determined whether the second data includes the token. In some aspects, a size of the IEEE 1149.1-compliant shift register is determined based on the second data.