Patents by Inventor Jae-Phil Kong
Jae-Phil Kong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10235312Abstract: A memory system includes a storage device and a host device. The storage device includes a memory device and a device controller. The device controller is configured to store device information. The device information includes a level of a power supply voltage required for the memory device. The host device includes a host controller and a power management integrated circuit (PMIC). The host device is configured to send a query command to receive the device information from the device controller during a power setting period. The PMIC is configured to supply a first level of power supply voltage to the memory device during the power setting period and, after the power setting period, selectively supply one of the first level of power supply voltage and a second level of power supply voltage to the memory device. The first level of power supply voltage is lower than the second level of power supply voltage.Type: GrantFiled: September 5, 2017Date of Patent: March 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Chang Cho, Jae-Phil Kong
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Publication number: 20180101492Abstract: A memory system includes a storage device and a host device. The storage device includes a memory device and a device controller. The device controller is configured to store device information. The device information includes a level of a power supply voltage required for the memory device. The host device includes a host controller and a power management integrated circuit (PMIC). The host device is configured to send a query command to receive the device information from the device controller during a power setting period. The PMIC is configured to supply a first level of power supply voltage to the memory device during the power setting period and, after the power setting period, selectively supply one of the first level of power supply voltage and a second level of power supply voltage to the memory device. The first level of power supply voltage is lower than the second level of power supply voltage.Type: ApplicationFiled: September 5, 2017Publication date: April 12, 2018Inventors: HEE-CHANG CHO, JAE-PHIL KONG
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Patent number: 9830993Abstract: A storage device includes a nonvolatile memory and a connector configured to connect the storage device to a host. The connector includes a detection terminal that provides a detection voltage to the host, a sensing resistor electrically connected to the detection terminal and having a resistance value that determines the level of the detection voltage, and a power supply terminal that receives a power supply voltage from the host, wherein the power supply voltage is selected by the host in response to the detection voltage.Type: GrantFiled: December 28, 2016Date of Patent: November 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Phil Kong, Hwa-Seok Oh
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Publication number: 20170206974Abstract: A storage device includes a nonvolatile memory and a connector configured to connect the storage device to a host. The connector includes a detection terminal that provides a detection voltage to the host, a sensing resistor electrically connected to the detection terminal and having a resistance value that determines the level of the detection voltage, and a power supply terminal that receives a power supply voltage from the host, wherein the power supply voltage is selected by the host in response to the detection voltage.Type: ApplicationFiled: December 28, 2016Publication date: July 20, 2017Inventors: JAE-PHIL KONG, HWA-SEOK OH
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Patent number: 9246515Abstract: An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.Type: GrantFiled: December 30, 2011Date of Patent: January 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Phil Kong, Seok-Won Ahn
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Patent number: 9037950Abstract: A memory controller and an operating method of the memory controller are provided. The operating method includes: performing error correction on data, including a plurality of chunks, in a unit of a chunk; determining if a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and controlling an output time of an error-corrected first chunk based on a result of the determining.Type: GrantFiled: December 26, 2012Date of Patent: May 19, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Phil Kong, Soong Mann Shin, Myung Suk Choi, Sin Ho Yang
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Patent number: 8990666Abstract: A decoder, a method of decoding and systems implementing the same are disclosed. In one example, the method includes calculating syndrome values from input codewords, generating an error location polynomial about the codewords using the syndrome values, determining an error count in the codewords using the error location polynomial, and adjusting power consumption of a circuit in response to the determined error count in the codewords. In one example, a frequency of a clock signal to be provided to a search circuit may be determined based on the error count, and the clock signal may be provided having the determined frequency to a search circuit, such as a Chien search circuit.Type: GrantFiled: September 15, 2011Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Phil Kong, Hwa Seok Oh, Dong Kim
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Publication number: 20130268803Abstract: A memory controller and an operating method of the memory controller are provided. The operating method includes: performing error correction on data, including a plurality of chunks, in a unit of a chunk; determining if a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and controlling an output time of an error-corrected first chunk based on a result of the determining.Type: ApplicationFiled: December 26, 2012Publication date: October 10, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Phil KONG, Soong Mann SHIN, Myung Suk CHOI, Sin Ho YANG
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Patent number: 8359424Abstract: Provided are a flash memory device and a reading method of the flash memory device. A multi-level cell flash memory device includes: a memory cell array comprising main memory cells storing main data, and indicator cells storing indicate data indicating one of a first mode and a second mode in which the main data of the main memory cell, to which the indicate cells correspond, is written; and an output unit outputting in response to a control signal corresponding to the indicate data, one of main data read from the memory cell array and forced data forcing some bit values of the main data to bit values of mode specific data, as reading data.Type: GrantFiled: November 12, 2009Date of Patent: January 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-phil Kong, Chi-weon Yoon
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Publication number: 20120173951Abstract: An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.Type: ApplicationFiled: December 30, 2011Publication date: July 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Phil Kong, Seok-Won Ahn
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Publication number: 20120072809Abstract: A decoder, a method of decoding and systems implementing the same are disclosed. In one example, the method includes calculating syndrome values from input codewords, generating an error location polynomial about the codewords using the syndrome values, determining an error count in the codewords using the error location polynomial, and adjusting power consumption of a circuit in response to the determined error count in the codewords. In one example, a frequency of a clock signal to be provided to a search circuit may be determined based on the error count, and the clock signal may be provided having the determined frequency to a search circuit, such as a Chien search circuit.Type: ApplicationFiled: September 15, 2011Publication date: March 22, 2012Inventors: Jae Phil Kong, Hwa Seok Oh, Dong Kim
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Publication number: 20100125699Abstract: Provided are a flash memory device and a reading method of the flash memory device. A multi-level cell flash memory device includes: a memory cell array comprising main memory cells storing main data, and indicator cells storing indicate data indicating one of a first mode and a second mode in which the main data of the main memory cell, to which the indicate cells correspond, is written; and an output unit outputting in response to a control signal corresponding to the indicate data, one of main data read from the memory cell array and forced data forcing some bit values of the main data to bit values of mode specific data, as reading data.Type: ApplicationFiled: November 12, 2009Publication date: May 20, 2010Inventors: Jae-phil Kong, Chi-weon Yoon
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Nonvolatile memory devices capable of reducing data programming time and methods of driving the same
Patent number: 7668015Abstract: In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.Type: GrantFiled: December 27, 2007Date of Patent: February 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-phil Kong, Heung-soo Lim, Jae-yong Jeong, Chi-weon Yoon -
Patent number: 7643340Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.Type: GrantFiled: November 28, 2007Date of Patent: January 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Phil Kong, Jae-Yong Jeong
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Patent number: 7447067Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.Type: GrantFiled: June 16, 2006Date of Patent: November 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Phil Kong, Jae-Yong Jeong
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Nonvolatile memory devices capable of reducing data programming time and methods of driving the same
Publication number: 20080192540Abstract: In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.Type: ApplicationFiled: December 27, 2007Publication date: August 14, 2008Inventors: Jae-Phil Kong, Heung-soo Lim, Jae-yong Jeong, Chi-weon Yoon -
Publication number: 20080068885Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.Type: ApplicationFiled: November 28, 2007Publication date: March 20, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Phil KONG, Jae-Yong JEONG
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Publication number: 20070035994Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.Type: ApplicationFiled: June 16, 2006Publication date: February 15, 2007Inventors: Jae-Phil Kong, Jae-Yong Jeong