Abstract: A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit, which includes sub peripheral circuits that are disposed under each sub cell array. Each sub peripheral circuit includes a sense amplifier region, which includes a plurality of bitline sense amplifiers, and a rest circuit region, which includes other circuits. First-type bitline sense amplifiers, which are connected to first-type bitlines, are disposed in the sense amplifier region of each sub peripheral circuit, and the first-type bitlines are disposed above the sense amplifier region of each sub peripheral circuit. Second-type bitline sense amplifiers, which are connected to second-type bitlines, are disposed in the sense amplifier region of a neighboring sub peripheral circuit adjacent in the column direction to a first sub peripheral circuit of the sub peripheral circuit, and the second-type bitlines are disposed above the rest region of each sub peripheral circuit.

Abstract: A semiconductor device includes a semiconductor substrate, an active region on the semiconductor substrate and including a first semiconductor material, an isolation layer on the semiconductor substrate and a side surface of the active region, a first gate structure in a first gate trench crossing the active region, a second gate structure in a second gate trench in the isolation layer, the second gate structure being parallel to the first gate structure and adjacent to the active region, a semiconductor layer covering at least a part of the side surface of the active region, the semiconductor layer including a second semiconductor material different from the first semiconductor material, and at least a part of the semiconductor layer being between the active region and the second gate structure, and source/drain regions in the active region on opposite sides of the first gate trench.

Abstract: A semiconductor device includes a lower structure, a data storage structure on the lower structure, and an inductor structure on the lower structure, where the data storage structure includes first electrodes extending in a vertical direction perpendicular to an upper surface of the lower structure, a second electrode provided on the first electrodes, and a dielectric layer between the first electrodes and the second electrode, and where the inductor structure includes an inductor conductive pattern at a level that is substantially the same as a level of the first electrodes.

Abstract: An integrated control apparatus for a vehicle according to an embodiment of the present disclosure includes a software component mapped onto each of a plurality of electronic control units (ECUs) for vehicle control and processing data of a corresponding ECU, and an aggregator that collects and analyzes diagnostic data regarding the ECU from the software component, generates error information about the corresponding ECU based on a predefined decoding table when an error occurs in the ECU, and transmits the error information to an external debugging apparatus.

Abstract: A transistor structure including an active pattern defined by a first isolation pattern on a substrate, a second isolation pattern at an upper portion of the active pattern, a gate structure extending through the active pattern and the first isolation pattern, at least a lower portion of the gate structure extending through the second isolation pattern, a first oxide semiconductor pattern on a lower surface and a sidewall of the gate structure, the first oxide semiconductor pattern including In-rich IGZO and at least partially contacting the first and second isolation patterns, and source/drain regions at upper portions of the active pattern adjacent to the gate structure may be provided.

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

Abstract: Disclosed is an austenitic stainless steel including, in percent by weight (wt %), 0.005 to 0.03% of C, 0.1 to 1% of Si, 0.1 to 2% of Mn, 0.01 to 0.4 of Cu, 0.01 to 0.2 of Mo, 6 to 9% of Ni, 16 to 19% of Cr, 0.01 to 0.2% of N, and the balance of Fe and inevitable impurities, wherein an austenitic stability parameter (ASP) value calculated by 551?462 (C+N)?9.2Si?8.1Mn?13.7Cr?29 (Ni+Cu)?18.5Mo is from 30 to 60, a [100*N]/[Ni+Cu] value is 1.4 or more, an average grain size is less than 5 ?m, and a fraction (%) of grains with a grain size of 5 ?m or more is less than 10%.

Abstract: A semiconductor device may include a substrate, an element layer including circuit elements arranged on the substrate, a wiring layer on the element layer, and a redistribution layer on the wiring layer. The redistribution layer may include a redistribution insulating layer and a redistribution conductive layer on the redistribution insulating layer. The redistribution conductive layer may include a connection pad and first and second inductor structures respectively including first and second inductor redistribution lines having a planar coil shape, and a connection pad. The first and second inductor redistribution lines respectively included in the first and second inductor structures may have different thicknesses.

Abstract: A semiconductor device includes a lower structure, a data storage structure on the lower structure, and an inductor structure on the lower structure, where the data storage structure includes first electrodes extending in a vertical direction perpendicular to an upper surface of the lower structure, a second electrode provided on the first electrodes, and a dielectric layer between the first electrodes and the second electrode, and where the inductor structure includes an inductor conductive pattern at a level that is substantially the same as a level of the first electrodes.

Abstract: A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit, which includes sub peripheral circuits that are disposed under each sub cell array. Each sub peripheral circuit includes a sense amplifier region, which includes a plurality of bitline sense amplifiers, and a rest circuit region, which includes other circuits. First-type bitline sense amplifiers, which are connected to first-type bitlines, are disposed in the sense amplifier region of each sub peripheral circuit, and the first-type bitlines are disposed above the sense amplifier region of each sub peripheral circuit. Second-type bitline sense amplifiers, which are connected to second-type bitlines, are disposed in the sense amplifier region of a neighboring sub peripheral circuit adjacent in the column direction to a first sub peripheral circuit of the sub peripheral circuit, and the second-type bitlines are disposed above the rest region of each sub peripheral circuit.

Abstract: A transistor structure including an active pattern defined by a first isolation pattern on a substrate, a second isolation pattern at an upper portion of the active pattern, a gate structure extending through the active pattern and the first isolation pattern, at least a lower portion of the gate structure extending through the second isolation pattern, a first oxide semiconductor pattern on a lower surface and a sidewall of the gate structure, the first oxide semiconductor pattern including In-rich IGZO and at least partially contacting the first and second isolation patterns, and source/drain regions at upper portions of the active pattern adjacent to the gate structure may be provided.

Abstract: A semiconductor device includes a semiconductor substrate, an active region on the semiconductor substrate and including a first semiconductor material, an isolation layer on the semiconductor substrate and a side surface of the active region, a first gate structure in a first gate trench crossing the active region, a second gate structure in a second gate trench in the isolation layer, the second gate structure being parallel to the first gate structure and adjacent to the active region, a semiconductor layer covering at least a part of the side surface of the active region, the semiconductor layer including a second semiconductor material different from the first semiconductor material, and at least a part of the semiconductor layer being between the active region and the second gate structure, and source/drain regions in the active region on opposite sides of the first gate trench.

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.

Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.

Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.

Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.

Abstract: A laser cutting device, including a laser beam generation unit emitting a laser beam; an optical system on a traveling path of the laser beam; a laser main body providing a passage through which the laser beam travels towards a substrate after passing through the optical system; a suction unit coupled to a header of the laser main body and sucking impurities, the suction unit including a curved surface therein; and a collection unit connected to the suction unit and collecting discharged impurities, the impurities being discharged to the collection unit along the curved surface inside the suction unit.

Abstract: A laser cutting device, including a laser beam generation unit emitting a laser beam; an optical system on a traveling path of the laser beam; a laser main body providing a passage through which the laser beam travels towards a substrate after passing through the optical system; a suction unit coupled to a header of the laser main body and sucking impurities, the suction unit including a curved surface therein; and a collection unit connected to the suction unit and collecting discharged impurities, the impurities being discharged to the collection unit along the curved surface inside the suction unit.

Abstract: Provided is a non-aqueous electrolyte-based, high-power lithium secondary battery having a long service life and superior safety at both room temperature and high temperature, even after repeated high-current charging and discharging. The battery comprises a mixture of a lithium/manganese spinel oxide having a substitution of a manganese (Mn) site with a certain metal ion and a lithium/nickel/cobalt/manganese composite oxide, as a cathode active material.