Patents by Inventor Jae Seok Heo
Jae Seok Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071262Abstract: An electronic price indicator according to an embodiment includes a display displaying product information, an NFC module configured to communicate with a user terminal, a Bluetooth module configured to communicate with the user terminal, and a processor configured to control the display to display the product information received from the user terminal through the Bluetooth module. The processor is further configured to release a sleep mode when receiving an interrupt from the user terminal through the NFC module, and perform Bluetooth communication with the user terminal by initiating a scan for a predetermined period of time to receive an advertising signal from the user terminal.Type: ApplicationFiled: January 20, 2023Publication date: February 29, 2024Inventors: Jae Gun HEO, Chung Hee LEE, Do Sang KWON, Woo Seok HAN, Chan LEE, Ji Hoon KIM, Bo II SEO
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Patent number: 11832537Abstract: The disclosed technology generally relates to a barrier layer comprising titanium silicon nitride, and more particularly to a barrier layer for nonvolatile memory devices, and methods of forming the same. In one aspect, a method of forming an electrode for a phase change memory device comprises forming over a semiconductor substrate an electrode comprising titanium silicon nitride (TiSiN) on a phase change storage element configured to store a memory state. Forming the electrode comprises exposing a semiconductor substrate to one or more cyclical vapor deposition cycles, wherein a plurality of the cyclical vapor deposition cycles comprises an exposure to a Ti precursor, an exposure to a N precursor and an exposure to a Si precursor.Type: GrantFiled: October 8, 2019Date of Patent: November 28, 2023Assignee: Eugenus, Inc.Inventors: Jae Seok Heo, Jerry Mack, Somilkumar J. Rathi, Niloy Mukherjee
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Publication number: 20220415709Abstract: The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.Type: ApplicationFiled: June 10, 2022Publication date: December 29, 2022Inventors: Niloy Mukherjee, Hae Young Kim, Jerry Mack, Jae Seok Heo, Sung-Hoon Jung, Somilkumar J. Rathi, Srishti Chugh, Nariman Naghibolashrafi, Yoshikazu Okuyama, Bunsen B. Nie
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Patent number: 11361992Abstract: The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.Type: GrantFiled: October 8, 2019Date of Patent: June 14, 2022Assignee: Eugenus, Inc.Inventors: Niloy Mukherjee, Hae Young Kim, Jerry Mack, Jae Seok Heo, Sung-Hoon Jung, Somilkumar J. Rathi, Srishti Chugh, Nariman Naghibolashrafi, Yoshikazu Okuyama, Bunsen B. Nie
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Publication number: 20210104665Abstract: The disclosed technology generally relates to a barrier layer comprising titanium silicon nitride, and more particularly to a barrier layer for nonvolatile memory devices, and methods of forming the same. In one aspect, a method of forming an electrode for a phase change memory device comprises forming over a semiconductor substrate an electrode comprising titanium silicon nitride (TiSiN) on a phase change storage element configured to store a memory state. Forming the electrode comprises exposing a semiconductor substrate to one or more cyclical vapor deposition cycles, wherein a plurality of the cyclical vapor deposition cycles comprises an exposure to a Ti precursor, an exposure to a N precursor and an exposure to a Si precursor.Type: ApplicationFiled: October 8, 2019Publication date: April 8, 2021Inventors: Jae Seok Heo, Jerry Mack, Somilkumar J. Rathi, Niloy Mukherjee
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Publication number: 20210104433Abstract: The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.Type: ApplicationFiled: October 8, 2019Publication date: April 8, 2021Inventors: Niloy Mukherjee, Hae Young Kim, Jerry Mack, Jae Seok Heo, Sung-Hoon Jung, Somilkumar J. Rathi, Srishti Chugh, Nariman Naghibolashrafi, Yoshikazu Okuyama, Bunsen B. Nie
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Patent number: 8779426Abstract: A thin film transistor for increasing the conductivity of a channel region and suppressing the leakage current of a back channel region, and a display device including the thin film transistor, are discussed. According to an embodiment, the thin film transistor includes a gate electrode arranged on a substrate, a source electrode and a drain electrode spaced from each other on the substrate, a gate insulating film to insulate the gate electrode from the source electrode and the drain electrode, and a semiconductor layer insulated from the gate electrode through the gate insulating film, the semiconductor layer including a channel region and a back channel region, the semiconductor layer made of (In2O3)x(Ga2O3)y(ZnO)z(0?x?5, 0?y?5, 0?z?5), wherein X or Z is greater than Y in the channel region of the semiconductor layer, and Y is greater than X and Z in the back channel region of the semiconductor layer.Type: GrantFiled: July 12, 2010Date of Patent: July 15, 2014Assignee: LG Display Co., Ltd.Inventors: Jae-Seok Heo, Ji-Yeon Seo
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Patent number: 8659094Abstract: An array substrate for a liquid crystal display device includes: a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode, the gate insulating layer including an organic insulating material such that a radical of carbon chain has a composition ratio of about 8% to about 11% by weight; a semiconductor layer on the gate insulating layer over the gate electrode; a data line crossing the gate line to define a pixel region; source and drain electrodes on the semiconductor layer, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole.Type: GrantFiled: May 23, 2011Date of Patent: February 25, 2014Assignee: LG Display Co., Ltd.Inventors: Byung-Geol Kim, Gee-Sung Chae, Jae-Seok Heo, Woong-Gi Jun
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Patent number: 8551825Abstract: A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs.Type: GrantFiled: June 8, 2011Date of Patent: October 8, 2013Assignee: LG Display Co., Ltd.Inventors: Bo Hyun Lee, Jae Seok Heo, Woong Gi Jun
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Patent number: 8129233Abstract: A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode; sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound; and forming source and drain electrodes at both sides of the semiconductor layer.Type: GrantFiled: January 25, 2010Date of Patent: March 6, 2012Assignee: LG Display Co., Ltd.Inventors: Woong Gi Jun, Gee Sung Chae, Jae Seok Heo
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Patent number: 8062924Abstract: A method for fabricating a TFT on a substrate includes forming a gate electrode; forming a semiconductor layer insulated from the gate electrode and partially overlapped with the gate electrode; forming a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a sol-gel compound; and forming source and drain electrodes at both sides of the semiconductor layer.Type: GrantFiled: February 1, 2010Date of Patent: November 22, 2011Assignee: LG Display Co., Ltd.Inventors: Gee Sung Chae, Jae Seok Heo, Woong Gi Jun
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Publication number: 20110237010Abstract: A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs.Type: ApplicationFiled: June 8, 2011Publication date: September 29, 2011Applicant: LG Display Co., Ltd.Inventors: Bo Hyun Lee, Jae Seok Heo, Woong Gi Jun
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Publication number: 20110220893Abstract: An array substrate for a liquid crystal display device includes: a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode, the gate insulating layer including an organic insulating material such that a radical of carbon chain has a composition ratio of about 8% to about 11% by weight; a semiconductor layer on the gate insulating layer over the gate electrode; a data line crossing the gate line to define a pixel region; source and drain electrodes on the semiconductor layer, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact holeType: ApplicationFiled: May 23, 2011Publication date: September 15, 2011Inventors: Byung-Geol Kim, Gee-Sung Chae, Jae-Seok Heo, Woong-Gi Jun
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Patent number: 7989242Abstract: An array substrate for a liquid crystal display device includes: a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode, the gate insulating layer including an organic insulating material such that a radical of carbon chain has a composition ratio of about 8% to about 11% by weight; a semiconductor layer on the gate insulating layer over the gate electrode; a data line crossing the gate line to define a pixel region; source and drain electrodes on the semiconductor layer, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole.Type: GrantFiled: December 19, 2008Date of Patent: August 2, 2011Assignee: LG Display Co., Ltd.Inventors: Byung-Geol Kim, Gee-Sung Chae, Jae-Seok Heo, Woong-Gi Jun
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Patent number: 7977676Abstract: A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs.Type: GrantFiled: December 27, 2006Date of Patent: July 12, 2011Assignee: LG Display Co., Ltd.Inventors: Bo Hyun Lee, Jae Seok Heo, Woong Gi Jun
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Publication number: 20110156021Abstract: A thin film transistor for increasing the conductivity of a channel region and suppressing the leakage current of a back channel region, and a display device including the thin film transistor, are discussed. According to an embodiment, the thin film transistor includes a gate electrode arranged on a substrate, a source electrode and a drain electrode spaced from each other on the substrate, a gate insulating film to insulate the gate electrode from the source electrode and the drain electrode, and a semiconductor layer insulated from the gate electrode through the gate insulating film, the semiconductor layer including a channel region and a back channel region, the semiconductor layer made of (In2O3)x(Ga2O3)y(ZnO)z(0?x?5, 0?y?5, 0?z?5), wherein X or Z is greater than Y in the channel region of the semiconductor layer, and Y is greater than X and Z in the back channel region of the semiconductor layer.Type: ApplicationFiled: July 12, 2010Publication date: June 30, 2011Inventors: Jae-Seok HEO, Ji-Yeon Seo
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Publication number: 20100140623Abstract: An array substrate for a display device includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode, the gate insulating layer having an organic-inorganic hybrid material; a semiconductor layer on the gate insulating layer over the gate electrode; source and drain electrodes spaced apart from each other on the semiconductor layer; a passivation layer on the source and drain electrodes, the passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole.Type: ApplicationFiled: November 10, 2009Publication date: June 10, 2010Inventors: Soon-Young MIN, Jae-Seok Heo
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Publication number: 20100136756Abstract: A method for fabricating a TFT on a substrate includes forming a gate electrode; forming a semiconductor layer insulated from the gate electrode and partially overlapped with the gate electrode; forming a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a sol-gel compound; and forming source and drain electrodes at both sides of the semiconductor layer.Type: ApplicationFiled: February 1, 2010Publication date: June 3, 2010Inventors: Gee Sung Chae, Jae Seok Heo, Woong Gi Jun
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Publication number: 20100136755Abstract: A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode; sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound; and forming source and drain electrodes at both sides of the semiconductor layer.Type: ApplicationFiled: January 25, 2010Publication date: June 3, 2010Inventors: Woong GI JUN, Gee Sung CHAE, Jae Seok HEO
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Patent number: 7683367Abstract: A method for fabricating a TFT on a substrate includes forming a gate electrode; forming a semiconductor layer insulated from the gate electrode and partially overlapped with the gate electrode; forming a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a sol-gel compound; and forming source and drain electrodes at both sides of the semiconductor layer.Type: GrantFiled: December 26, 2006Date of Patent: March 23, 2010Assignee: LG Display Co., Ltd.Inventors: Gee Sung Chae, Jae Seok Heo, Woong Gi Jun