Abstract: A phased array antenna includes a transmission unit of a first layer including a plurality of first plates having a polygonal profile, a reception unit of a second layer including a plurality of second plates having a polygonal profile, the reception unit being spaced apart from the transmission unit in a first direction, and a circuit unit arranged within an internal space defined by the transmission unit and the reception unit.

Abstract: An ultra-high frequency power combiner according to the disclosure includes a first input line connected to a first input port, a second input line connected to a second input port, an output line connected to an output port, a first transmission line between the first input line and the output line, a second transmission line between the second input line and the output line, a first series capacitor, a resistor, and a second series capacitor connected in series between a first node between the first input line and the first transmission line and a second node between the second input line and the second transmission line, and a first parallel capacitor, an inductor, and a second parallel capacitor connected in parallel with the resistor and connected in series with one another.

Abstract: A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.

Abstract: A phased array antenna includes a transmission unit of a first layer including a plurality of first plates having a polygonal profile, a reception unit of a second layer including a plurality of second plates having a polygonal profile, the reception unit being spaced apart from the transmission unit in a first direction, and a circuit unit arranged within an internal space defined by the transmission unit and the reception unit.

Abstract: An ultra-high frequency power combiner according to the disclosure includes a first input line connected to a first input port, a second input line connected to a second input port, an output line connected to an output port, a first transmission line between the first input line and the output line, a second transmission line between the second input line and the output line, a first series capacitor, a resistor, and a second series capacitor connected in series between a first node between the first input line and the first transmission line and a second node between the second input line and the second transmission line, and a first parallel capacitor, an inductor, and a second parallel capacitor connected in parallel with the resistor and connected in series with one another.

Abstract: A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.

Abstract: A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.

Abstract: A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.