Patents by Inventor Jae-Soon Kwon

Jae-Soon Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130049094
    Abstract: A method for fabricating a non-volatile memory device includes forming a gate layer over a substrate having a cell region and a peripheral circuit region, forming a gate pattern corresponding to a region for selection lines and a region between neighboring selection lines in the cell region, where during the forming of the gate pattern, word lines in the cell region and a peripheral circuit gate in the peripheral circuit region are formed by selectively etching the gate layer, forming spacers on sidewalls of the peripheral circuit gate, and forming the selection lines by selectively etching a portion of the gate pattern corresponding to the region between the neighboring selection lines.
    Type: Application
    Filed: December 21, 2011
    Publication date: February 28, 2013
    Inventor: Jae-Soon KWON
  • Patent number: 6780774
    Abstract: Disclosed herein is a method of semiconductor device isolation, which forms a device isolation film on an isolation region of a substrate using a trench process. The method comprises the steps of providing a semiconductor substrate where a device isolation region was defined; forming a mask on the substrate in such a manner that the device isolation region is exposed through the mask; etching the substrate using the mask to form a trench; thermally treating an inner wall of the trench using the mask under a hydrogen atmosphere; forming a first insulating layer covering the resulting inner wall of the trench; forming a second insulating layer on the mask in such a manner that the second insulating film covers the first insulating film; firstly etching the second insulating layer to expose a surface of the mask; removing the mask; secondly etching the remaining second insulating layer until a surface of the substrate is exposed, thereby forming a device isolation film.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: August 24, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Soon Kwon
  • Publication number: 20030064597
    Abstract: Disclosed herein is a method of semiconductor device isolation, which forms a device isolation film on an isolation region of a substrate using a trench process. The method comprises the steps of providing a semiconductor substrate where a device isolation region was defined; forming a mask on the substrate in such a manner that the device isolation region is exposed through the mask; etching the substrate using the mask to form a trench; thermally treating an inner wall of the trench using the mask under a hydrogen atmosphere; forming a first insulating layer covering the resulting inner wall of the trench; forming a second insulating layer on the mask in such a manner that the second insulating film covers the first insulating film; firstly etching the second insulating layer to expose a surface of the mask; removing the mask; secondly etching the remaining second insulating layer until a surface of the substrate is exposed, thereby forming a device isolation film.
    Type: Application
    Filed: December 21, 2001
    Publication date: April 3, 2003
    Inventor: Jae Soon Kwon
  • Patent number: 6194257
    Abstract: A method of fabricating a gate electrode having dual gate insulating film includes the steps of sequentially providing a substrate having a first portion and a second portion, forming a first insulating film on the first portion of substrate, a first conductive film on the first insulating film and a second insulating film on the first conductive film, forming a third insulating film on the second portion of the substrate, forming a second conductive film on the second and the third insulating films, and patterning the first and the second conductive film to form a gate electrode.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: February 27, 2001
    Assignee: LG Semicon Co., Ltd.
    Inventor: Jae-Soon Kwon
  • Patent number: 5966609
    Abstract: A semiconductor device and a fabrication method thereof which are capable of enhancing the electrostatic capacity of a capacitor and preventing a short channel effect which occurs due to the decrease of a channel width.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: October 12, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Jae-Soon Kwon