Patents by Inventor Jaesun An

Jaesun An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip package and manufacturing method thereof
    Patent number: 8592958
    Abstract: A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: November 26, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Dongkyun Ko, Jung Lee, Jaesun An
  • CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20120098109
    Abstract: A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.
    Type: Application
    Filed: December 8, 2011
    Publication date: April 26, 2012
    Inventors: Dongkyun Ko, Jung Lee, Jaesun An
  • Chip package and manufacturing method thereof
    Patent number: 8093690
    Abstract: A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: January 10, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Dongkyun Ko, Jung Lee, Jaesun An
  • CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20100110656
    Abstract: A chip package including a plurality of conductive bodies and a shielding layer for better electromagnetic interferences shielding is provided. The shielding layer over the molding compound contacts with the conductive bodies disposed on the substrate, and the shielding layer and the conductive bodies function as EMI shield. The shielding layer is electrically grounded through the conductive bodies connected to the laminate substrate and the ground plane of the substrate.
    Type: Application
    Filed: February 19, 2009
    Publication date: May 6, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Dongkyun Ko, Jung Lee, Jaesun An
  • CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20100109132
    Abstract: A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.
    Type: Application
    Filed: March 31, 2009
    Publication date: May 6, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Dongkyun Ko, Jung Lee, Jaesun An