Patents by Inventor Jae-Sun Yun
Jae-Sun Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9263576Abstract: Provided is a semiconductor device. The semiconductor device includes an insulating layer extending in a first direction. A first vertical channel pillar is disposed separately from the insulating layer. A first interconnection line extends in a second direction perpendicular to the first direction, and is electrically connected to the first vertical channel pillar. A first bit line extends in the second direction, and crosses over the first interconnection line and the first vertical channel pillar. A first bit contact overlaps the first interconnection line, and electrically connects the first interconnection line to the first bit line. A length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.Type: GrantFiled: December 19, 2014Date of Patent: February 16, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Gn Yun, Hoo-Sung Cho, Jae-Sun Yun
-
Publication number: 20150380549Abstract: Provided is a semiconductor device. The semiconductor device includes an insulating layer extending in a first direction. A first vertical channel pillar is disposed separately from the insulating layer. A first interconnection line extends in a second direction perpendicular to the first direction, and is electrically connected to the first vertical channel pillar. A first bit line extends in the second direction, and crosses over the first interconnection line and the first vertical channel pillar. A first bit contact overlaps the first interconnection line, and electrically connects the first interconnection line to the first bit line. A length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.Type: ApplicationFiled: December 19, 2014Publication date: December 31, 2015Inventors: JANG-GN YUN, HOO-SUNG CHO, JAE-SUN YUN
-
Patent number: 8767462Abstract: The nonvolatile memory device may include a substrate including a first region and a second region. A string line group may be disposed on the substrate in the first region, and a bias interconnection group may be disposed above the substrate in the second region. The bias interconnection group may include a string select bias interconnection, cell bias interconnections, and a ground select bias interconnection, which may be respectively electrically connected to a string select line, word lines, and a ground select line of the string line group. The string select bias interconnection may be disposed between the ground select bias interconnection and the cell bias interconnections of the bias interconnection group.Type: GrantFiled: March 23, 2011Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Jae-Sun Yun
-
Publication number: 20110249497Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a substrate including a first region and a second region, which are spaced from each other. A string line group is disposed on the substrate in the first region, and a bias interconnection group is disposed above the substrate in the second region. The bias interconnection group includes a string select bias interconnection, cell bias interconnections, and a ground select bias interconnection, which are respectively electrically connected to a string select line, word lines, and a ground select line within the string line group. The string select bias interconnection is disposed between the ground select bias interconnection and the cell bias interconnections within the bias interconnection group.Type: ApplicationFiled: March 23, 2011Publication date: October 13, 2011Inventor: Jae-sun Yun
-
Patent number: 7920021Abstract: A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.Type: GrantFiled: October 16, 2009Date of Patent: April 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Yong Oh, Sang-youn Jo, Joon-hee Lee, Jae-sun Yun, Seong-soo Kim
-
Publication number: 20100207690Abstract: A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.Type: ApplicationFiled: October 16, 2009Publication date: August 19, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-Yong Oh, Sang-youn Jo, Joon-hee Lee, Jae-sun Yun, Seong-soo Kim
-
Patent number: 7518210Abstract: Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.Type: GrantFiled: January 31, 2005Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Sun Yun, Jin-Hyun Shin
-
Patent number: 6969650Abstract: Gate structures of a non-volatile integrated circuit memory device can include a thermal oxidation layer on a substrate beneath the gate structure that defines a side wall of the gate structure. An oxygen diffusion barrier layer is on the side wall of the gate structure and a floating gate is on the thermal oxidation layer and has a curved side wall portion. Related methods are also discussed.Type: GrantFiled: July 29, 2003Date of Patent: November 29, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-sun Yun, Jin-hyun Shin
-
Patent number: 6939780Abstract: Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.Type: GrantFiled: June 24, 2003Date of Patent: September 6, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Sun Yun, Jin-Hyun Shin
-
Publication number: 20050127472Abstract: Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.Type: ApplicationFiled: January 31, 2005Publication date: June 16, 2005Inventors: Jae-Sun Yun, Jin-Hyun Shin
-
Publication number: 20040072408Abstract: Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.Type: ApplicationFiled: June 24, 2003Publication date: April 15, 2004Inventors: Jae-Sun Yun, Jin-Hyun Shin
-
Publication number: 20040046206Abstract: Gate structures of a non-volatile integrated circuit memory device can include a thermal oxidation layer on a substrate beneath the gate structure that defines a side wall of the gate structure. An oxygen diffusion barrier layer is on the side wall of the gate structure and a floating gate is on the thermal oxidation layer and has a curved side wall portion. Related methods are also discussed.Type: ApplicationFiled: July 29, 2003Publication date: March 11, 2004Inventors: Jae-Sun Yun, Jin-Hyun Shin
-
Patent number: 6153469Abstract: An improved method of fabricating a flash memory cell is disclosed. A tunnel oxide film is formed on active regions. A first conductive film and a protective film are sequentially formed on the tunnel oxide film. The protective film on the isolation film is selectively etched, thus forming a protective film pattern on the tunnel oxide film. A sacrificial conductive film is formed on the resultant structure. The sacrificial conductive film and the first conductive film pattern are over-etched until the sidewalls and the upper surface of the protective film pattern are exposed, thereby exposing the center of the isolation film and simultaneously forming a first conductive film pattern having sloped sidewalls. With the present invention, an electrical field is prevented from being concentrated in an area between a control gate electrode and a floating gate because the floating gate have a sloped sidewall profile instead of sharp edges.Type: GrantFiled: July 13, 1999Date of Patent: November 28, 2000Assignee: Samsung Electronics, Co., Ltd.Inventors: Jae-sun Yun, Jeong-hyuk Choi, Chan-jo Lee