Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.

Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on the body and connected to the internal electrode layer. At least one hole is formed in the internal electrode layer, and a region, containing at least one selected from the group consisting of indium (In) and tin (Sn), is disposed in the hole. A method of manufacturing a capacitor component includes forming a dielectric green sheet, forming a conductive thin film, including a first conductive material and a second conductive material, on the dielectric green sheet, and sintering the conductive thin film to form an internal electrode layer. The internal electrode layer includes the first conductive material, and a region, including the second conductive material, is formed in the internal electrode layer.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.

Abstract: An infusion flow regulator includes: a main body having an inlet through which fluid is introduced and an outlet through which the fluid is discharged; and a rotary dial rotatably coupled to the main body, with a sealing member interposed therebetween, so as to regulate a flow rate of the fluid, in which the rotary dial includes a regulating flow path having a shape of a recessed groove in cross section with a first width and a first height, and the regulating flow path includes a first region in which the first width is constant and the first height is decreased, and a second region in which both the first width and the first height are decreased. By the aforementioned configuration, the infusion flow regulator for the fluid can accurately regulate the flow rate even in a region where the flow rate of the fluid is very small.

Abstract: A display driving device including: a gate driver configured to provide a first gate selection signal to a first gate line of a display panel to select the first gate line; a source driver configured to provide an image signal corresponding to the first gate line to a source line; an Electrostatic Discharge (ESD) detection circuit configured to receive a power supply voltage, determine whether there is an ESD in the power supply voltage and, when the ESD is detected, generate a first detection signal; and a controller configured to receive the first detection signal to generate a masking signal, wherein the gate driver is configured to receive the masking signal and not provide a second gate selection signal to select a second gate line.

Abstract: A display driving device including: a gate driver configured to provide a first gate selection signal to a first gate line of a display panel to select the first gate line; a source driver configured to provide an image signal corresponding to the first gate line to a source line; an Electrostatic Discharge (ESD) detection circuit configured to receive a power supply voltage, determine whether there is an ESD in the power supply voltage and, when the ESD is detected, generate a first detection signal; and a controller configured to receive the first detection signal to generate a masking signal, wherein the gate driver is configured to receive the masking signal and not provide a second gate selection signal to select a second gate line.

Abstract: The common voltage generator includes an operational amplifier and a plurality of switches. The operational amplifier is configured to amplify a difference between a first voltage and a second voltage and to output the amplified voltage as a common voltage. The plurality of switches are configured to transmit a third voltage and a fourth voltage as a power supply to the operational amplifier in a first voltage output mode and to transmit a fifth voltage and a sixth voltage as a power supply to the operational amplifier in a second voltage output mode.

Abstract: A switching circuit and a DC-DC converter including the same are provided. The switching circuit includes an output terminal, a plurality of input terminals, and a plurality of switches configured to selectively connect the plurality of input terminals to the output terminal. The plurality of switches include a first switch directly connected to the output terminal and a plurality of second switches connecting the plurality of input terminals to the first switch. The first switch is implemented using a high-voltage transistor. Each of the second switches is implemented using a low-voltage transistor. A gate of the high-voltage transistor is at least two times longer than a gate of the low-voltage transistor. The DC-DC converter increases or decreases a signal selected from among a plurality of input signals input through the input terminals by a predetermined voltage level.

Abstract: A voltage generator that prevents latch-up includes: a charge pump circuit that is controlled by first through third enable signals, boosts an internal power voltage generated from an external power voltage, and generates first through fourth voltages; a detector that detects the first through third voltages and generates first through third flag signals that go logic high when the first through third voltages reach predetermined respective voltage levels and maintain logic low when the voltages do not reach the predetermined respective voltage levels; and a charge pump controller that receives the first through third flag signals, and generates the first through third enable signals to have the first through fourth voltages sequentially generated. The voltage generator can prevent latch-up that may occur in a boosting mode or in a normal operation mode.

Abstract: A display driving integrated circuit (IC) capable of reducing the number of transmission lines for transmitting gray-scale data from a memory. The display driving IC receives M-bit gray-scale data to represent the gray scale of one pixel and drives a panel including a plurality of pixels. The display driving IC includes a memory storing gray-scale data representing the gray scales of the plurality of pixels, a source driver receiving the gray-scale data from the memory through transmission lines and transmitting the received gray-scale data to the panel, and at least one multiplexer to transmit the M-bit gray-scale data representing the gray scale of one pixel through L transmission lines, wherein the value of L is smaller than the value of M.

Abstract: Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.

Abstract: A switching circuit and a DC-DC converter including the same are provided. The switching circuit includes an output terminal, a plurality of input terminals, and a plurality of switches configured to selectively connect the plurality of input terminals to the output terminal. The plurality of switches include a first switch directly connected to the output terminal and a plurality of second switches connecting the plurality of input terminals to the first switch. The first switch is implemented using a high-voltage transistor. Each of the second switches is implemented using a low-voltage transistor. A gate of the high-voltage transistor is at least two times longer than a gate of the low-voltage transistor. The DC-DC converter increases or decreases a signal selected from among a plurality of input signals input through the input terminals by a predetermined voltage level.

Abstract: A source driver having a small layout area and low power consumption includes a signal generation block generating a plurality of pulse width modulation (PWM) signals and a plurality of staircase waveform grayscale voltage signals according to a digital code generated based on an oscillation signal and a channel driver. The channel driver divides latched video data into upper bits and lower bits, generates a plurality of switching signals using one PWM signal selected from among the plurality of PWM signals in response to the lower bits, outputs one staircase waveform grayscale voltage signal selected from among the plurality of staircase waveform grayscale voltage signals in response to the upper bits, and outputs a particular grayscale voltage level included in the one staircase waveform grayscale voltage signal in response to the plurality of switching signals.

Abstract: The common voltage generator includes an operational amplifier and a plurality of switches. The operational amplifier is configured to amplify a difference between a first voltage and a second voltage and to output the amplified voltage as a common voltage. The plurality of switches are configured to transmit a third voltage and a fourth voltage as a power supply to the operational amplifier in a first voltage output mode and to transmit a fifth voltage and a sixth voltage as a power supply to the operational amplifier in a second voltage output mode.

Abstract: A charge pump circuit and related method are provided. The charge pump circuit includes first, second and third voltage generation units, first and second control units, and a latch-up prevention unit. The first generation unit regulates a first output signal, the second generation unit boosts a second output signal, and the third generation unit boosts a third output signal in response to the first and second output signals. The first control unit is connected between the first generation unit and the third generation unit, and the second control unit is connected between the second generation unit and the third generation unit. The first and second control units block respective outputs of the first and second generation units during the boosting time for the second output signal. The latch-up prevention unit prevents a latch-up operation caused by a parasitic transistor until the third output signal is maintained at a third voltage.

Abstract: A broadcast playback method includes receiving a first format of a broadcast stream transmitted by a broadcast station over a first radio network, playing the first format of the broadcast stream through demodulation and decoding processes, receiving a second format of the broadcast stream over a second radio network when the first radio network is unavailable, and playing the second format of the broadcast stream.

Abstract: A program guide data decoding method for a digital broadcast receiver includes detecting a request to decode structural data including a data unit and decoding the structural data using a template that matches the structure of the data unit when the matching template exists.

Abstract: A voltage generator that prevents latch-up includes: a charge pump circuit that is controlled by first through third enable signals, boosts an internal power voltage generated from an external power voltage, and generates first through fourth voltages; a detector that detects the first through third voltages and generates first through third flag signals that go logic high when the first through third voltages reach predetermined respective voltage levels and maintain logic low when the voltages do not reach the predetermined respective voltage levels; and a charge pump controller that receives the first through third flag signals, and generates the first through third enable signals to have the first through fourth voltages sequentially generated. The voltage generator can prevent latch-up that may occur in a boosting mode or in a normal operation mode.

Abstract: A charge pump circuit and related method are provided. The charge pump circuit includes first, second and third voltage generation units, first and second control units, and a latch-up prevention unit. The first generation unit regulates a first output signal, the second generation unit boosts a second output signal, and the third generation unit boosts a third output signal in response to the first and second output signals. The first control unit is connected between the first generation unit and the third generation unit, and the second control unit is connected between the second generation unit and the third generation unit. The first and second control units block respective outputs of the first and second generation units during the boosting time for the second output signal. The latch-up prevention unit prevents a latch-up operation caused by a parasitic transistor until the third output signal is maintained at a third voltage.