Abstract: A method of a first terminal may include: identifying first RB set(s) to be used for SL communication among consecutive RB sets through an LBT procedure; identifying a first subchannel group included in the first RB set(s) and a second subchannel group including a first PRB in the first RB set(s), the first PRB being not included in the first subchannel group; configuring the first PRB within the second subchannel group as an SL communication resource; and transmitting, to a second terminal, control information indicating that the first PRB is configured as the SL communication resource.

Abstract: A semiconductor device manufacturing method includes providing a first layer having a first surface, providing a second layer including a trench that exposes the first surface, onto the first layer, forming a first polymer layer that fills the trench, and performing a heat treatment process on the first polymer layer to form a second polymer layer. A second surface of the second layer is exposed by the trench, the first polymer layer includes a first portion being in contact with the first surface, and a second portion being in contact with the second surface, when the heat treatment process is performed, the first portion of the first polymer layer is decomposed, when the heat treatment process is performed, the second portion of the first polymer layer is cross-linked to form the second polymer layer, and physical properties of the first layer are different from physical properties of the second layer.

Abstract: Compositions for manufacturing a thin film are provided. The compositions may include a compound having a structure of Chemical Formula 1: M may be strontium (Sr) or barium (Ba), X1 and X2 may each independently be oxygen (O) or a substituted or unsubstituted alkylamino group having 1 to 5 carbon atoms, R1 and R2 may each independently be a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms or a substituted or unsubstituted perfluoro alkyl group having 1 to 5 carbon atoms, R3 may be hydrogen or a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms, L may be a substituted or unsubstituted polyether having 1 to 6 oxygen atoms, or a substituted or unsubstituted polyamine having 1 to 6 nitrogen atoms, or a substituted or unsubstituted polyetheramine having 1 to 6 oxygen atoms or nitrogen atoms, and n may be an integer of 1 to 6.

Abstract: An apparatus for constructing a library for deriving a material composition using empirical result, which enables acceleration of research on the material-properties relationship. By applying the empirical results of the material composition, missing data of the material compositions can be statistically calculated by using supervised non-linear imputation techniques. The completed composition information of the materials is passed as an input of machine learning material-properties relationship prediction.

Abstract: A nonvolatile memory device includes an operation control unit, a reference voltage generating unit, and a sensing unit. The operation control unit is configured to select a unit cell from unit cells to perform reading and writing operations. The reference voltage generating unit is configured to voltage-divide a read voltage using series-connected resistors and generate a reference voltage based on the voltage-divided read voltage. The sensing unit is configured to compare a size of a voltage through an e-fuse of the selected unit cell based on the read voltage with the reference voltage, and sense data of the e-fuse of the selected unit cell. The nonvolatile memory device also includes a read current supply unit configured to output the read voltage to the unit cells during a reading operation of the nonvolatile memory device.

Abstract: A nonvolatile memory device includes an operation control unit, a reference voltage generating unit, and a sensing unit. The operation control unit is configured to select a unit cell from unit cells to perform reading and writing operations. The reference voltage generating unit is configured to voltage-divide a read voltage using series-connected resistors and generate a reference voltage based on the voltage-divided read voltage. The sensing unit is configured to compare a size of a voltage through an e-fuse of the selected unit cell based on the read voltage with the reference voltage, and sense data of the e-fuse of the selected unit cell. The nonvolatile memory device also includes a read current supply unit configured to output the read voltage to the unit cells during a reading operation of the nonvolatile memory device.

Abstract: A three-dimensional foaming type transfer paper with an enhanced durability and a method for manufacturing the same is disclosed. The transfer paper includes a releasing agent layer having a releasing sheet and formed on the releasing sheet using transparent silicon; a fluorine coating layer formed on the releasing agent layer; a silicon rubber layer formed only on a portion of the fluorine coating layer on which printing is to be performed, through a silk screen process; a first fluoride polyester layer formed on the silicon rubber layer; a printed layer formed on the first fluoride polyester layer using ink; a second fluoride polyester layer formed on the printed layer; a first foaming layer formed partially on the second fluoride polyester layer; a second foaming layer formed on the first foaming layer; and a thermal adhesive resin layer formed on the second foaming layer.

Abstract: A semiconductor memory device suitable for rapidly transferring output data from sense amplifiers to an output-buffer is disclosed. The semiconductor memory device includes a plurality of sense amplifiers respectively connected to a plurality of cell blocks. A first common output-line is connected to a first set of sense amplifiers associated with a first set of cell blocks. A second common output-line is connected to a second set of sense amplifiers associated with a second set of cell blocks. A loading selection circuit selects one of the first and second common output-lines so as to transfer output data from a selected sense amplifier, via the selected one of the first and second common output-lines, to another device, such as an output-buffer.

Abstract: The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor wafer and a fabrication method of semiconductor chips. According to the present invention, a semiconductor wafer containing a plurality of semiconductor chip portions has a plurality of chip scribe lanes formed between the semiconductor chip portions. A plurality of chip bonding pads are formed on the semiconductor chip portions of the wafer, and a plurality of wafer probing pads are formed on the chip scribe lanes. The wafer probing pads are electrically connected to internal circuits of the semiconductor chip portions and/or to corresponding ones of the chip bonding pads.

Abstract: A semiconductor memory device suitable for rapidly transferring output data from sense amplifiers to an output-buffer is disclosed. The semiconductor memory device includes a plurality of sense amplifiers respectively connected to a plurality of cell blocks. A first common output-line is connected to a first set of sense amplifiers associated with a first set of cell blocks. A second common output-line is connected to a second set of sense amplifiers associated with a second set of cell blocks. A loading selection circuit selects one of the first and second common output-lines so as to transfer output data from a selected sense amplifier, via the selected one of the first and second common output-lines, to another device, such as an output-buffer.

Abstract: A data output buffer is disclosed that includes an input section receiving a data signal and an output enable signal to output a pull-up signal and a pull-down signal, a drive control section and a plurality of output driving sections. The drive control section activates less than all of the plurality of drive control signals in response to the data signal in a second mode and activates all the drive control signals in normal operations or a first mode. The plurality of output driving sections each receive the pull-up signal, the pull-down signal and one of the drive control signals to perform a pull-up operation or pull-down operation in accordance with the logic value of the data signal when activated.

Abstract: A semiconductor memory includes a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells outputs a first data signal through an I/O line; an I/O line driving circuit for generating a second data signal by amplifying the first data signal, wherein the I/O line driving circuit is connected to the I/O lines; a data bus driving circuit connected to the I/O line driving circuit to generate a third data signal by amplifying the second data signal; a data bus precharge circuit; and a data bus connecting the data bus driving circuit to the data bus precharge circuit, wherein the data bus precharge circuit precharges the data bus to a predetermined voltage level before the third data signal is generated and transfers a voltage of the data bus to high or low level in accordance with a logic value of the third data signal when the third data signal is generated.

Abstract: A semiconductor memory includes a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells outputs a first data signal through an I/O line; an I/O line driving circuit for generating a second data signal by amplifying the first data signal, wherein the I/O line driving circuit is connected to the I/O lines; a data bus driving circuit connected to the I/O line driving circuit to generate a third data signal by amplifying the second data signal; a data bus precharge circuit; and a data bus connecting the data bus driving circuit to the data bus precharge circuit, wherein the data bus precharge circuit precharges the data bus to a predetermined voltage level before the third data signal is generated and transfers a voltage of the data bus to high or low level in accordance with a logic value of the third data signal when the third data signal is generated.

Abstract: The present invention relates to a semiconductor memory circuit capable of reducing the number of routes to decrease the area of a chip. In a construction of a synchronous semiconductor memory circuit with a LOC architecture in accordance with the present invention including a peripheral circuit block in which an address pad and an input/output pad are arranged at the left and right sides of a chip, respectively, an address counter is placed at the center of the address pad, a first address decoder is placed at the address pad, a second address decoder is placed at the input/output pad, a first address counter buffer for driving the first address decoder upon receipt of the output of the address counter is placed adjacent to the address counter between the address counter and the first address decoder, and a second address counter buffer for driving the second address decoder upon receipt of the output of the address counter is placed at the center of the chip.

Abstract: An input buffer circuit for a semiconductor device includes a first input buffer unit having first and second transistors, a second input buffer unit coupled to the first input buffer unit, the second input buffer unit having third and fourth transistors, a control unit for activating one of the first and second input buffer units, and a switching unit having fifth, sixth, and seventh transistors and coupled to the control unit.

Abstract: The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor wafer and a fabrication method of semiconductor chips. According to the present invention, a semiconductor wafer containing a plurality of semiconductor chip portions has a plurality of chip scribe lanes formed between the semiconductor chip portions. A plurality of chip bonding pads are formed on the semiconductor chip portions of the wafer, and a plurality of wafer probing pads are formed on the chip scribe lanes. The wafer probing pads are electrically connected to internal circuits of the semiconductor chip portions and/or to corresponding ones of the chip bonding pads.

Abstract: An improved voltage level detecting circuit that provides stable voltage detection. The voltage level detecting circuit senses a level of a voltage to be detected only when two clock signals are at a low level after ORing the signals. After detecting the voltage level, the circuit reduces power consumption by preventing a current path between the voltage and ground. Consistent operation of the voltage level detecting circuit is achieved despite fluctuation of the voltage level to be detected caused by noise through detecting the level of the voltage only when a specific clock signal is enabled.

Abstract: A pulse extending circuit includes a pulse extension inverting device for extending an input pulse signal by a predetermined width; and a delay device for extending the signal output from the pulse extension inverting device; thereby increasing a delay effect.

Abstract: An input buffer circuit of a semiconductor memory capable of controlling a logic threshold voltage of the circuit according to a change in an external supply voltage, which includes an external supply voltage detecting unit for dividing the external supply voltage into a plurality of regions by comparing a plurality of voltages, which have been divided by different ratios of the entire external supply voltage, with a standard voltage; and a converting unit including a pull-up circuit and a pull-down circuit, for converting input signals of TTL level into signals of CMOS level, according to the regions of the external supply voltage obtained by the external supply voltage detecting unit.