Abstract: A method of generating a virtual address in a data processing system controller includes receiving and analyzing attribute information which indicates whether user intervention is possible for allocating a memory buffer for storing image data; enabling one of a first virtual address generator or a second virtual address generator based on an analysis result; and generating the virtual address of a data transaction using the enabled virtual address generator.

Abstract: A coherent interconnect is provided. The coherent interconnect includes a snoop filter and a circuit that receives a write request, strobe bits, and write data from a central processing unit (CPU); generates a snoop filter request based on the write request; and transmits, at substantially the same time, the snoop filter request to the snoop filter and the write request, the strobe bits, and the write data to a memory controller.

Abstract: An application processor is provided. The application processor includes a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and a master-side filter connected between the cache coherent interconnect and the second master device. The master-side filter receives a snoop request from the first master device through the cache coherent interconnect, compares a second security attribute of the second master device with a first security attribute of the first master device which is included in the snoop request, and determines whether to transmit an address included in the snoop request to the second master device according to a comparison result.

Abstract: Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection.

Abstract: A method of generating a virtual address in a data processing system controller includes receiving and analyzing attribute information which indicates whether user intervention is possible for allocating a memory buffer for storing image data; enabling one of a first virtual address generator or a second virtual address generator based on an analysis result; and generating the virtual address of a data transaction using the enabled virtual address generator.

Abstract: A coherent interconnect is provided. The coherent interconnect includes a snoop filter and a circuit that receives a write request, strobe bits, and write data from a central processing unit (CPU); generates a snoop filter request based on the write request; and transmits, at substantially the same time, the snoop filter request to the snoop filter and the write request, the strobe bits, and the write data to a memory controller.

Abstract: An application processor is provided. The application processor includes a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and a master-side filter connected between the cache coherent interconnect and the second master device. The master-side filter receives a snoop request from the first master device through the cache coherent interconnect, compares a second security attribute of the second master device with a first security attribute of the first master device which is included in the snoop request, and determines whether to transmit an address included in the snoop request to the second master device according to a comparison result.

Abstract: A method of rotating an original image includes performing a self-learning using addresses related to at least one page miss and generating address generation rules using a result of the self-learning. The method includes pre-fetching the original image from a memory device based on the address generation rules to obtain a pre-fetched image and generating a rotated image using the pre-fetched image.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A bus system includes a plurality of master devices each of which issues a transaction request having a first transaction identifier with a first bit width and a slave device responding to the transaction request having a second transaction identifier with a second bit width and supplying a transaction response having the second transaction identifier to the plurality of master devices. The embodiment further comprises a bus configured to connect one of the plurality of master devices and the slave device; and an ID converter configured to connect the bus and the slave device and to map the first transaction identifier to the second transaction identifier for providing the second transaction identifier to the slave device and map the second transaction identifier to the first transaction identifier for providing the first transaction identifier to the one of the plurality of master devices.

Abstract: Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A method of rotating an original image includes performing a self-learning using addresses related to at least one page miss and generating address generation rules using a result of the self-learning. The method includes pre-fetching the original image from a memory device based on the address generation rules to obtain a pre-fetched image and generating a rotated image using the pre-fetched image.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A system on chip (SoC) and a method of operating the same are provided. The SoC includes a central processing unit (CPU) controlling a memory operation and a display operation on a current frame of an image based on generation of the image and an interrupt signal; an image generator requesting data of the current frame from a memory according to control of the CPU; a UD unit determining whether the current frame is updated, detecting whether an update region is a partial frame based on virtual addresses included in a request of the image generator, and outputting the interrupt signal corresponding to the update region to the CPU; a memory controller storing the update region in the memory according to the control of the CPU; and a display controller accessing the memory and outputting the update region to a display device according to the control of the CPU.

Abstract: A method of operating an address generator configured to map an image onto a plurality of memories via an interleaving includes detecting information associated with the image and the interleaving; selecting an address mapping scheme according to the detection result; and mapping the image onto the plurality of memories according to the selected address mapping scheme.

Abstract: A bus system includes a plurality of master devices each of which issues a transaction request having a first transaction identifier with a first bit width and a slave device responding to the transaction request having a second transaction identifier with a second bit width and supplying a transaction response having the second transaction identifier to the plurality of master devices. The embodiment further comprises a bus configured to connect one of the plurality of master devices and the slave device; and an ID converter configured to connect the bus and the slave device and to map the first transaction identifier to the second transaction identifier for providing the second transaction identifier to the slave device and map the second transaction identifier to the first transaction identifier for providing the first transaction identifier to the one of the plurality of master devices.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: The present invention relates to an elevator traction machine, and more particularly, to an elevator traction machine, wherein a plurality of planetary gears are coupled to be circumscribed and engaged with a sun gear formed at one end of a driven shaft in order to reduce high speed rotation transmitted from a driving motor and to wind wires on a sheave, and pinions formed at the other sides of the planetary gears are circumscribed and engaged with a plurality of other planetary gears or a fixed sun gear so that planetary gears just before the fixed sun gear can be rotated together with a flange, thereby obtaining reduction effects for a gear ratio among the sun gears, pinions and planetary gears, and noise/vibration-reducing effects and large rotational force-transmitting effects due to formation of the gears out of helical gears.

Abstract: The present invention relates to a wind generator. The wind generator comprises a body installed freely rotatably at a tower, blades installed at a leading end of the body, a gearbox for receiving rotational forces from the blades, and a generator connected to the gearbox for generating electricity. The blades are coupled with a blade angle adjustment unit so that the angles of the blades can be adjusted at predetermined angles according to the directions and velocities of winds. The gearbox comprises a planet gear coupled with a rotational shaft of the blades, a ring gear which has teeth formed on a radially inner surface thereof and engages with the planet gears, and a sun gear which engages with the planet gear and is connected with the generator. Teeth are formed on a radially outer surface of the ring gear so that teeth of a stop gear can be engaged therewith.