Abstract: A method and apparatus for monitoring and controlling power to a device such as a PCMCIA/PC card. A PCMCIA/PC card adapter is provided for communicating data and control signals to and from a PCMCIA/PC card and a host processor. The PCMCIA/PC card adapter may communicate with the PCMCIA/PC card to determine the correct voltage(s) for the PCMCIA/PC card. The PCMCIA/PC card may then communicate instruct a power control circuit to provide an appropriate voltage to the PCMCIA/PC card. The power control circuit may be provided with status monitoring registers containing status data reflecting monitored conditions of the PCMCIA/PC card and power supply. A System Management Bus (SMB) may link the power control circuit and the PCMCIA/PC card adapter. If an abnormal status is detected in the PCMCIA/PC card or power supply (e.g.

Abstract: A method and arrangement for controlling input/output (I/O) operations in a computer system provides multiple PC card controllers but allows legacy software to be used. A PCI bus is coupled to a central processing unit, and an ISA bus is coupled to the PCI bus by a bridge. At least one PC card controller is coupled to the PCI bus and at least one other PC card controller is coupled to the ISA bus. Each PC card controller has at least one socket in which a device is connectable, each socket being separately addressable by the processor at an (I/O) address through the respect PC card controller. Each controller also has a socket pointer register, each socket pointer register being loadable with socket pointer information that uniquely identifies each socket of the controller among all of the sockets of the plurality of controllers in the computer system. Each controller also has an index register and a plurality of data registers, the index stored in the index register pointing to one of the data registers.

Abstract: A peripheral device capable of generating interrupt request signals compliant with the Industry Standard Architecture (ISA) protocol, and the Peripheral Component Interconnect (PCI) protocol. The peripheral device comprises a signal generator block which selectively generates either the interrupt request signals of the PCI protocol or a set of bits representative of interrupt request signals of the ISA protocol. The set of bits are transferred serially to a converter circuit which generates the interrupt request signals of the ISA protocol based on the bits. The signal generator block generates bits in such a way as to support both pulse mode and level mode interrupt request signals for the ISA protocol.