Abstract: An apparatus, system, and method for improved replica bit line (RBL) operation are provided. An memory control circuit can include an RBL including a plurality of replica bit cells (RBCs) electrically coupled in series, a timer and control logic circuit situated to receive an output of the RBL, and a first multiplexer electrically coupled between the RBL and the timer and control logic circuit, the first multiplexer configured to set a replica word line (RWL) that controls, based on a state of select lines input into the first multiplexer and input provided by the timer and control logic, which of the RBCs is active.

Abstract: An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1->0) ST CLK # based on PCLK assertion (0->1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.

Abstract: Embodiments herein relate to optimizing the duration of a sense amp enable signal in a memory device such as SRAM. A control circuit asserts the sense amp enable signal in response to a clock signal from a replica column of the SRAM. A feedback path extends from the sense amps back to the control circuit. In one approach, a change in a feedback signal on the feedback path indicates the sense amps have all received the sense amp enable signal. In another approach, a change in a feedback signal on the feedback path indicates the sense amps have all completed their sensing operations. In some cases, a selection can be made among multiple feedback paths.

Abstract: A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.