Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.

Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.

Abstract: An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

Abstract: An electronic device includes a processor, the processor having a cache memory, a set of physical registers, and a promotion logic functional block. When one or more promotion conditions are met, the promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory to a physical register among the set of physical registers.

Abstract: In a computer system having multiple memory proximity domains including a first memory proximity domain with a first processor and a first memory and a second memory proximity domain with a second processor and a second memory, latencies of memory access from each memory proximity domain to its local memory as well as to memory at other memory proximity domains are probed. When there is no contention, the local latency will be lower than remote latency. If the contention at the local memory proximity domain increases and the local latency becomes large enough, memory pages associated with a process running on the first processor are placed in the second memory proximity domain, so that after the placement, the process is accessing the memory pages from the memory of the second memory proximity domain during execution.

Abstract: An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

Abstract: In a computer system having multiple memory proximity domains including a first memory proximity domain with a first processor and a first memory and a second memory proximity domain with a second processor and a second memory, latencies of memory access from each memory proximity domain to its local memory as well as to memory at other memory proximity domains are probed. When there is no contention, the local latency will be lower than remote latency. If the contention at the local memory proximity domain increases and the local latency becomes large enough, memory pages associated with a process running on the first processor are placed in the second memory proximity domain, so that after the placement, the process is accessing the memory pages from the memory of the second memory proximity domain during execution.