Patents by Inventor Jagadish Rongali

Jagadish Rongali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-way cache memory access
    Patent number: 11544199
    Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: January 3, 2023
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Bassam S. Kamand, Waleed Younis, Ramon Zuniga, Jagadish Rongali
  • MULTI-WAY CACHE MEMORY ACCESS
    Publication number: 20220066942
    Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.
    Type: Application
    Filed: October 12, 2021
    Publication date: March 3, 2022
    Inventors: Bassam S. Kamand, Waleed Younis, Ramon Zuniga, Jagadish Rongali
  • Multi-way cache memory access
    Patent number: 11176051
    Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 16, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Bassam S. Kamand, Waleed Younis, Ramon Zuniga, Jagadish Rongali
  • MULTI-WAY CACHE MEMORY ACCESS
    Publication number: 20210286732
    Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Bassam S. Kamand, Waleed Younis, Ramon Zuniga, Jagadish Rongali