Abstract: Embodiments herein relate to techniques to facilitate a user to enable one or more smart battery charging algorithms on a device to control charging of a battery associated with the device. A control circuitry of the device may receive usage data associated with a battery of the device (e.g., via a battery interface). The control circuitry may predict a future health metric of the battery based on the usage data. The control circuitry may compare the future metric to a threshold and trigger, based on the comparison, display of information about one or more smart charging algorithms to the user. Additionally, or alternatively, the control circuitry may generate predicted performance information associated with multiple charging configurations and present the performance information to the user. Other embodiments may be described and claimed.

Abstract: Some examples provide battery charging techniques that allow for reasonably fast charging while reducing charging temperature. In some examples, a target temperature limit is actively maintained through a control loop. In some examples, CC charge phases are interleaved with CV stages.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for magnetic connectors with asymmetric attach/detach mechanism. An example electronic device disclose herein includes a port having an opening to receive a connector and a magnet array associated with the port. The magnet array includes a first magnet, and a second magnet. The electronic device includes a spring to bias at least one of the first magnet or second magnet away from the opening.

Abstract: Techniques for system power control based on a battery's thermal limit and impedance are described. In certain examples, a system includes: a hardware processor that includes a continuous boost power mode; and a power management circuit to couple to a battery, wherein the power management circuit is to: determine heat dissipation for the battery over time when the hardware processor is in the continuous boost power mode, and control power provided to the hardware processor in the continuous boost power mode without exceeding a limit of the heat dissipation over time.

Abstract: Embodiments of the present disclosure are directed to low-profile battery cells. For example, in some embodiments may include multiple cell tabs coupled to cathode and anode layers that are wound, such that the tabs are offset when jelly rolled. Other embodiments may be described and claimed.

Abstract: A computing system having a high-performance battery pack (e.g., 3S, 4S battery packs) coupled to a voltage regulator and logic to control an input supply of the voltage regulator. The logic determines the context of usage of the computing device (or user attentiveness) and either dynamically bypasses the voltage regulator to provide the voltage from the high-performance battery pack directly to various components of the computing system, or dynamically engages devices of the voltage regulator to provide a lower supply voltage to the various components of the computing system.

Abstract: A power architecture that uses an efficient intermediate power conversion stage between AC adaptor (and battery charger) and subsequent voltage regulators (VRs) (e.g., core VR) for processors for higher overall efficiency allowing for higher performance in a given thermal envelope and iso-system input power. Power losses from both the charger and the core VR are reduced by splitting the power as power to sustained high-power rails, and power to the rest of the platform power rails that have low residency in high-power states. The sustained high-power rails are placed under an intermediate power conversion topology which is directly powered by the adaptor. The rest of the rails along with charging of the battery are powered by the battery charger.