Patents by Inventor Jagannath Chirravuri
Jagannath Chirravuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11153162Abstract: A multi-function communications network includes a front-end communications network in signal communication with a plurality of communication nodes. Each communication node includes a plurality of discrete network elements. One or more network element adapters are in signal communication with a respective network element among the plurality of discrete network elements. A network management system is in signal communication with the network element adapters. The network management system is configured to generate reconfiguration parameters in response to an operating disruption of at least one affected node among the plurality of communication nodes. At least one of the network elements included in the affected node is reconfigured based at least in part on the reconfiguration parameters.Type: GrantFiled: May 31, 2019Date of Patent: October 19, 2021Assignee: RAYTHEON COMPANYInventors: Jagannath Chirravuri, John P. Denorscia, Richard William Smith, Marina Gurevich, Michael Gibbons
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Patent number: 11023625Abstract: A computational accelerator architecture facilitates change management of works in a model-based system engineering (MBSE) system in which each of the MBSE works includes a plurality of separately-identifiable statements. A linkage data store stores statement-wise, variable-strength linkages between certain statements of the MBSE works, where the linkages are indicative of associations between those certain statements. A revision control engine detects changes made to statements of MBSE works, and selectively indicates calls for revision of other statements in response to those changes based on respective strengths of linkages associated with the changed statements.Type: GrantFiled: January 10, 2019Date of Patent: June 1, 2021Assignee: Raytheon CompanyInventors: Christopher R. Eck, Cassandra L. Wellman, Jagannath Chirravuri
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Publication number: 20200382368Abstract: A multi-function communications network includes a front-end communications network in signal communication with a plurality of communication nodes. Each communication node includes a plurality of discrete network elements. One or more network element adapters are in signal communication with a respective network element among the plurality of discrete network elements. A network management system is in signal communication with the network element adapters. The network management system is configured to generate reconfiguration parameters in response to an operating disruption of at least one affected node among the plurality of communication nodes. At least one of the network elements included in the affected node is reconfigured based at least in part on the reconfiguration parameters.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Inventors: Jagannath Chirravuri, John P. Denorscia, Richard William Smith, Marina Gurevich, Michael Gibbons
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Publication number: 20200226220Abstract: A computational accelerator architecture facilitates change management of works in a model-based system engineering (MBSE) system in which each of the MBSE works includes a plurality of separately-identifiable statements. A linkage data store stores statement-wise, variable-strength linkages between certain statements of the MBSE works, where the linkages are indicative of associations between those certain statements. A revision control engine detects changes made to statements of MBSE works, and selectively indicates calls for revision of other statements in response to those changes based on respective strengths of linkages associated with the changed statements.Type: ApplicationFiled: January 10, 2019Publication date: July 16, 2020Inventors: Christopher R. Eck, Cassandra L. Wellman, Jagannath Chirravuri
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Patent number: 5436996Abstract: A waferboard assembly incorporates mechanical registration features into a substrate platform to facilitate the passive alignment of lasers integrated on a chip to fibers in integral contact with the substrate. The waferboard includes two front pedestal structures and one side pedestal structure, and two vertical post structures within a mounting region defined by the pedestal struutures. The laser chip is mounted on the vertical post structures, and placed in concurrent abutting contact with the pedestal structures. The waferboard is fabricated by etching the substrate to form the front and side pedestal structures, and etching the substrate to define the grooves. In order to form the post structures, a polyimide material is deposited on the substrate using an appropriate mask.Type: GrantFiled: September 28, 1994Date of Patent: July 25, 1995Assignee: GTE Laboratories IncorporatedInventors: Marvin Tabasky, Victor Cataldo, Thomas W. Fitzgerald, Jagannath Chirravuri, Craig A. Armiento, Paul O. Haugasjaa
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Patent number: 5287216Abstract: A fiber optic amplifier is disclosed utilizing a doped fiber to provide amplification through stimulated emission. The doped fiber is simultaneously pumped by multiple pump lasers generating optical waves of differing wavelengths. The optical waves from the lasers are combined using a wavelength division multiplexer before introduction into the doped fiber. The use of multiple pump lasers decreases the power requirements of each laser, reduces the cost of the amplifier, and increases reliability without compromising the gain of the amplifier.Type: GrantFiled: December 16, 1992Date of Patent: February 15, 1994Assignee: GTE Laboratories IncorporatedInventors: Jagannath Chirravuri, Ta-Sheng Wei, William J. Miniscalco
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Patent number: 5268066Abstract: A waferboard assembly incorporates mechanical registration features into a substrate platform to facilitate the passive alignment of lasers integrated on a chip to fibers in integral contact with the substrate. The waferboard includes two front pedestal structures and one side pedestal structure, and two vertical post structures within a mounting region defined by the pedestal structures. The laser chip is mounted on the vertical post structures, and placed in concurrent abutting contact with the pedestal structures. The waferboard is fabricated by etching the substrate to form the front and side pedestal structures, and etching the substrate to define the grooves. In order to form the post structures, a polyimide material is deposited on the substrate using an appropriate mask.Type: GrantFiled: December 30, 1992Date of Patent: December 7, 1993Assignee: GTE Laboratories IncorporatedInventors: Marvin Tabasky, Victor Cataldo, Thomas W. Fitzgerald, Jagannath Chirravuri, Craig A. Armiento, Paul O. Haugsjaa
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Patent number: 5261017Abstract: Apparatus for improving the coupling efficiency of a laser to a single mode fiber by means of an intermediate waveguide is disclosed. For uniform waveguides maximum improvement results when waveguide's mode field radii MFR is designed as the geometrical mean of the MFR of the laser and the MFR of the fiber. The apparatus can be extended to multi-stage couplers. Each successive stage is designed to have a spot size which is the geometric mean of the section before and after. With only a small number of stages significant improvement in coupling efficiency can be realized.Type: GrantFiled: November 17, 1992Date of Patent: November 9, 1993Assignee: GTE Laboratories IncorporatedInventors: Paul Melman, Jagannath Chirravuri
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Patent number: 5182782Abstract: A waferboard assembly incorporates mechanical registration features into a substrate platform to facilitate the passive alignment of lasers integrated on a chip to fibers in integral contact with the substrate. The waferboard includes two front pedestal structures and one side pedestal structure, and two vertical post structures within a mounting region defined by the pedestal structures. The laser chip is mounted on the vertical post structures, and placed in concurrent abutting contact with the pedestal structures. The waferboard is fabricated by etching the substrate to form the front and side pedestal structures, and etching the substrate to define the grooves. In order to form the post structures, a polyimide material is deposited on the substrate using an appropriate mask.Type: GrantFiled: January 7, 1992Date of Patent: January 26, 1993Assignee: GTE Laboratories IncorporatedInventors: Marvin Tabasky, Victor Cataldo, Thomas W. Fitzgerald, Jagannath Chirravuri, Craig A. Armiento, Paul O. Haugsjaa