Abstract: An asynchronous transfer mode switch includes a switching engine with a set of buffer groups having a set of 1-cell buffers where a cell is stored in only one buffer. The number of buffer groups exceeds the number of input ports. The switching engine also comprises a buffer management module, which includes a FIFO memory to maintain a pool of buffer groups that have at least one available buffer and memory to store bit maps for each buffer group and to store a CNT field value for each buffer to indicate which of its buffers are available to store a new cell, and which buffers still contain a cell that have not yet been read by its destination ports. The bit maps and CNT field values are updated during buffer allocation and buffer reads so that the FIFO maintains a current list of all buffer groups having available buffers.

Abstract: An asynchronous transfer mode packet switch for use in a Broadband Integrated Services Digital Network is disclosed. The asynchronous transfer mode packet switch is highly modular and allows expansion of the switch to handle applications having less than eight input and output devices to applications having up to 2.sup.14 input and output devices. The preferred asynchronous transfer mode packet switch is constructed as either a single-stage switch for routing data packets between up to 2.sup.6 input and output devices, a two-stage switch for routing packets between up to 2.sup.10 input and output devices, or a three-stage switch for routing packets between up to 2.sup.14 input and output devices.

Abstract: A concurrent echo cancellation and channel equalization signal processor for hybrid full duplex communication, including a decision device and three transversal adaptive filters, in which the gain coefficients of the three transversal filters are adjusted in accordance with a fast Kalman algorithm to minimize the error between the estimated far end signal after it has passed through a hybrid (produced by summing the filter outputs) and the estimated received far end signal (produced by the decision device).

Abstract: Speech bit rate reduction by robbing, e.g. periodically not transmitting, a percentage of speech data samples in a communication system employing differential pulse code modulation (DPCM) or adaptive differential pulse code modulation (ADPCM). To overcome feedback interference introduced in the code by sample robbing, a robbed sample is replaced by its estimate so that the coding process continues in a normal manner. The estimate is established on the basis of autocorrelation statistics of the speech data samples. At the receiving end of the communication system, the robbed sample is estimated by the same process and re-estimated again using delayed interpolation after one period of delay. The technique is particularly useful where graceful degradation is desired under heavy traffic loading on the data channel, and is found most beneficial when the bit rate is about 24kb/s or lower where a relatively larger quantizing noise masks the interpolation noise introduced by sample robbing.