Abstract: A transceiver system includes a clock generator and an analog-to-digital circuit (ADC). The transceiver system also includes a coupling correction circuit coupled to the clock generator and to the ADC, wherein the coupling correction circuit is configured to provide an in-phase correction and a quadrature-phase correction to a signal received by the ADC.

Abstract: A system includes a Zero IF transmitter having a mixer and a programmable gain stage. The Zero IF transmitter also includes an intermediate stage between the mixer and the programmable gain stage, wherein the intermediate stage is configured to decouple the mixer and the programmable gain stage.

Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.

Abstract: A non-linearity correction module, an optional droop corrector, and a zero-IF receiver with the non-linearity correction module and an optional droop corrector, wherein the non-linearity correction module is configured to generate a non-linearity term scaled to mitigate an inter-modulation component term of a RF signal received by the zero-IF receiver based on a test signal to enhance linearity in the zero-IF receiver and the optional droop corrector is configured to compensate a droop within a signal band of interest, caused by an analog low pass filter filtering a RF signal received by the zero-IF receiver, before a down-converted RF signal is fed into the non-linearity module.

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

Abstract: A transceiver system includes a clock generator and an analog-to-digital circuit (ADC). The transceiver system also includes a coupling correction circuit coupled to the clock generator and to the ADC, wherein the coupling correction circuit is configured to provide an in-phase correction and a quadrature-phase correction to a signal received by the ADC.

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

Abstract: A circuit includes first and second operational amplifiers, each including positive and negative inputs and first and second internal nodes. A mixer couples first and second input nodes to the positive and negative inputs of the operational amplifiers. The mixer switches the first and second input nodes between the positive and negative inputs of the first and second operational amplifiers in accordance with clock signals. A first cancellation capacitor couples to the first input node, and a second cancellation capacitor couple to the second input node. First and second switches selectively couple the first cancellation capacitor to the first and second internal nodes, respectively, of the first operational amplifier. Third and fourth switches selectively couple the second cancellation capacitor to the first and second internal nodes, respectively, of the second operational amplifier.

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

Abstract: The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.

Abstract: A bio-sensing device (and method) calibrates a time period used to make bio-physical measurements. The device initiates a light source sense phase followed by a first ambient sense phase and a second ambient sense phase. In the light source sense phase, the device is configured to receive a digital value indicative of current through a photodetector while the light source circuit is enabled and in each of the first and second ambient sense phases, the device is configured to receive digital values while the light source circuit is disabled. The device iteratively varies the time period between the phases until the digital value received during the first ambient sense phase is within a threshold of the digital value received during the second ambient sense phase. It then applies the same time separation between the light source sense phase and the ambient phase thereby equalizing the magnitude of the ambient light in the two phases.

Abstract: A comparator includes a differential input pair of transistors, a pair of cross coupled n-channel metal-oxide-semiconductor field-effect (NMOS) transistors, a pair of p-channel metal-oxide semiconductor field-effect (PMOS) transistors, a first inverter, and a second inverter. The differential input pair of transistors includes a first input transistor and a second input transistor. The pair of cross coupled NMOS transistors includes a first NMOS transistor and a second NMOS transistor. The pair of PMOS transistors includes a first PMOS transistor and a second PMOS transistor. The pair of PMOS transistors are coupled to the pair of cross coupled NMOS transistors. The first inverter is coupled in series with the first PMOS transistor. The second inverter is coupled in series with the second PMOS transistor.

Abstract: The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

Abstract: A direct conversion radio frequency receiver comprising: a clock generator to provide a first clock signal and a second clock signal; a first node; a second node; a zero-intermediate frequency (zero-IF) mixer coupled to the first and second nodes, clocked by the first and second clock signals, and comprising a first transimpedance amplifier and a second transimpedance amplifier to provide a direct-conversion voltage; a current injector, coupled to the first and second nodes, configurable to inject into the first and second nodes a common mode current or a differential mode current; and a controller, coupled to the zero-IF mixer and the current injector, to adjust at least one of the first and second transimpedance amplifiers based on the direct-conversion voltage when the current injector is to inject the common mode current.

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

Abstract: At least some embodiments are directed to a light detection system comprising a photodiode, a transimpedance amplifier (TIA) having a differential output and a differential input coupled across the photodiode, a first bias current source coupled to an anode of the photodiode, and a second bias current source coupled to a cathode of the photodiode. The system also comprises a dynamic control logic coupled to the first and second bias current sources and configured to vary bias currents provided by the first and second bias current sources based on the differential output such that the photodiode is reverse-biased.

Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source coupled between a first set of input switches. An impedance network is coupled between the first set of input switches and a first set of output switches. The impedance network includes a body impedance and a plurality of electrode impedances. A sense circuit is coupled to the first set of output switches. The sense circuit measures the body impedance and at least one electrode impedance of the plurality of electrode impedances.

Abstract: The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.