Patents by Inventor Jagat Patel

Jagat Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240330562
    Abstract: A plurality of design iterations are executed for a flow to design a circuit. The design flow includes a sequence of at least two stages. Each stage produces an output design of the circuit from an input design of the circuit, in accordance with parameters for that stage. The design iterations select parameter values for slices of one or more stages of the design flow. In the design iterations for at least one of the slices, parameter values for a non-final stage of the design flow are selected based on a final quality of result (QoR) of the design flow. The design iterations for this slice are adapted based on final QoRs produced by the design iterations.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Inventors: Piyush Verma, Joseph Robb Walston, Robert Lawrence Walker, Pranay Prakash, Jagat Patel, Mark Thomas Williams, Navneedh Shivakumar Maudgalya, Benoit Claudel
  • Patent number: 6574788
    Abstract: A method and system for automatically generating low level design tool commands as dependency graphs from abstracted high level physical design stages. The novel system inputs names of blocks of a hierarchical integrated circuit. Each block name has associated with it certain variables, stages and conditional statements. The stages represent a set of linked physical design processes that are to be executed on the block. Stages can be dependent on other stages and therefore are executed in-order on the block depending on how they are linked in the input set. The system automatically generates, from the input set, a dependency graph for each block. The dependency graph includes a large volume of nodes with associated parameters and options. Each node includes one or more low level program commands (“tasks”) for directing a number of physical design tools, e.g., programs, to perform various functions with respect to the block. Each node can receive input and generate an output.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: June 3, 2003
    Assignee: ReShape, Inc.
    Inventors: Margie Levine, Peter Dahl, Byron Dickinson, Jagat Patel, Paul Rodman