Abstract: A Thermal Ball Lead Integrated Package (Thermal BLIP) having improved thermal performance over prior art BLIPs is described. The BLIP combines ball and lead technologies to increase the interconnect density of the package but has relatively poor heat extraction capabilities. The Thermal BLIP is particularly well suited for high power and pin count integrated circuit devices. In an embodiment of the present invention, a heat sink is attached to the top surface of the die and extends through the package molding such that it is exposed to the ambient environment. Since the heat sink is integrated into the molding, the package size and footprint is not increased thereby limiting the cost increase of the package. This arrangement enables the use of high power devices in dense circuit board applications.

Abstract: An integrated circuit package assembly incorporating an electrostatic discharge (ESD) interposer is disclosed. The assembly includes a semiconductor chip including a plurality of chip input/output terminals. The interposer is formed using a substrate which supports the chip and includes an arrangement having a plurality of integrally formed ESD protection circuits for providing ESD protection to predetermined ones of the chip input/output terminals.

Abstract: A method of manufacturing an integrated circuit package assembly including (i) an integrated circuit die having a bottom surface and a plurality of input/output terminals, (ii) electrically conductive traces and/or contacts accessible from outside the assembly, and (iii) an encapsulating material encapsulating the integrated circuit die and portions of the electrically conductive traces and/or contacts will be disclosed. The method includes the following steps. First, a temporary support substrate or carrier having a top surface is provided for supporting the integrated circuit package as the package is being assembled. Then, the integrated circuit die is detachably supported on the top surface of the temporary support substrate. Each of the input/output terminals on the integrated circuit die are electrically connected to the electrically conductive traces and/or contacts.

Abstract: A CERDIP housing is provided with a heat pipe that passes through the closure seal lid whereby the heat pipe terminates within the housing cavity at the hot end thereof. A quantity of working fluid, such as fluorinated octane, is contained within the package cavity. The heat pipe communicates with cooling fins that produce a cold end thereof. Heat from the semiconductor device inside the housing boils the working fluid and is cooled thereby. The fluid vapor passes along the heat pipe and is condensed at the cold end to be converted back to liquid. As a result the semiconductor device is in direct communication with the heat pipe working fluid.

Abstract: A solder composition of 10 to 40 percent tin, with the balance lead, for use in thin layers of 50 to 500 microinches on copper integrated circuit leads so as to resist the formation of intermetallics when later heated.

Abstract: In a process for fabricating semiconductor devices having a patterned polyimide (PI) or polyimide-iso-indroquinazalinedione (PIQ) insulating layer on the device, a layer of uncured PI or PIQ resin is applied on a surface of the device. The resin layer is heated to produce a first level of partial curing in the resin layer. A photoresist is applied to the partially cured resin layer where it is to be removed. The partially cured resin layer is etched to produce the patterned layer. The patterned layer is then heated to produce a second level of partial cure, sufficient to prevent organic photoresist strippers from attacking the patterned layer. The developed photoresist is then stripped with an organic photoresist stripper, and the patterned layer heated a third time a sufficient extent to complete the curing of the PI and PIQ resin. The process desirably uses etching compositions comprising an amine etchant having the formula R--CH.sub.2 --CH.sub.2 --NH.sub.