Abstract: A computer system for determining whether or not a tool for deploying a software patch should be invoked is provided. The system may include a receiver that receives information regarding patch deployment over a first pre-determined amount of time. The system may include a processor configured to determine, based on the historical information, a patch deployment index. The patch deployment index may characterize patch deployment as a number of patches deployed per unit time. The receiver may receive historical information regarding patch deployment over a second amount of time. The processor may use the historical information regarding patch deployment of the second pre-determined amount of time to determine a second patch deployment index. The processor may compare the first deployment to the second patch deployment index. When the difference between the second index and the first index is greater than a pre-determined threshold, the processor may invoke the tool.

Abstract: A computer system for determining whether or not a tool for deploying a software patch should be invoked is provided. The system may include a receiver that receives information regarding patch deployment over a first pre-determined amount of time. The system may include a processor configured to determine, based on the historical information, a patch deployment index. The patch deployment index may characterize patch deployment as a number of patches deployed per unit time. The receiver may receive historical information regarding patch deployment over a second amount of time. The processor may use the historical information regarding patch deployment of the second pre-determined amount of time to determine a second patch deployment index. The processor may compare the first deployment to the second patch deployment index. When the difference between the second index and the first index is greater than a pre-determined threshold, the processor may invoke the tool.

Abstract: A line driver circuit is disclosed which may comprise a first supply voltage potential node; a second supply voltage potential node; a latch node; a first transistor of a first conductivity type and having a source coupled to the first supply voltage potential node, a drain coupled to the latch node, and a gate; a second transistor of the first conductivity type and having a source coupled to the first supply voltage potential node, a drain coupled to the gate of the first transistor of the first conductivity type, and a gate coupled to the latch node; a first transistor of a second conductivity type opposite to the first conductivity type and having a drain coupled to the drain of the second transistor of the first conductivity type, a source coupled to the second supply voltage potential node and a gate coupled to the latch node; and a diode having an anode coupled to the input node and a cathode coupled to the second supply voltage potential node.

Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.

Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

Abstract: A memory device includes a memory cell whose data state is sensed by a sense amplifier. A balance amplifier having the same construction as the sense amplifier is utilized to sense a balance cell having the same construction as the memory cell. The balance cell is maintained in an erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit is used to adjust the conductivity of the of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.

Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories. The bit line voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.

Abstract: A zero power fuse circuit includes a latch means having two inputs, a first input being latched to ground and a second input being latched to V.sub.cc. The latch means is triggered either by a momentary contact of the first input to ground or by the momentary contact of the second input to V.sub.cc. A first embodiment includes two fuse element/capacitor pairs each coupled to one of the two inputs of the latch means. A second embodiment includes a pull-up transistor and a fuse element/capacitor pair, coupled to the first and second inputs respectively. A third embodiment includes a pull-down transistor and a fuse element/capacitor pair respectively coupled to the second and first inputs of the latch means.

Abstract: An improved method of programming flash EEPROM devices is provided, wherein the time required to write a plurality of data bytes to a flash EEPROM device with verification is substantially reduced. The disclosed method significantly reduces the effects of the settling times on the overall program-verification cycle by performing row verification of the programmed data bytes instead of the byte verification associated with conventional verification operations.

Abstract: A memory device is provided that includes a plurality of floating gate memory cells arranged in an array, where each memory cell includes a control gate, a drain and a source. A decoder is provided that applies a first erase voltage to the control gates of selected floating gate memory cells of the array to prevent erasure of the selected floating gate memory cells and a second erase voltage to the control gates of the remaining floating gate memory cells of the array to permit erasure of the remaining floating gate memory cells in a sector erase mode of operation. The decoder is also preferably capable of supplying the second erase voltage to the control gates of each of the floating gate memory cells in a bulk erase mode of operation.

Abstract: An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.

Abstract: An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.

Abstract: The invention pertains to a circuit for controlling the power to a plurality of sense amplifiers used for sensing data on data lines in an array of floating gate storage cells, wherein the data stored in the array is sensed at regular intervals. The circuit includes a first plurality of data paths through the array, and a second data path containing replications of all necessary circuit elements in the first plurality of data paths to assure that the data delay through the second path equals or exceeds the maximum delay in any of the first plurality of data paths. A clock is used to provide an initiation signal which starts the propagation of input data through the array. A means is coupled to the clock for sending a dummy data pulse through the second data path upon receipt of the initiation signal, and a detecting means detects the completion of the passage of the dummy data through the second path and supplies a completion signal in response.