Patents by Inventor Jagdish Saraswatula

Jagdish Saraswatula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Guided scanning electron microscopy metrology based on wafer topography
    Patent number: 10957608
    Abstract: A wafer topography measurement system can be paired with a scanning electron microscope. A topography threshold can be applied to wafer topography data about the wafer, which was obtained with the wafer topography measurement system. A metrology sampling plan can be generated for the wafer. This metrology sampling plan can include locations in the wafer topography data above the topography threshold. The scanning electron microscope can scan the wafer using the metrology sampling plan and identify defects.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 23, 2021
    Assignee: KLA-Tencor Corporation
    Inventors: Arpit Yati, Shivam Agarwal, Jagdish Saraswatula, Andrew Cross
  • Guided Metrology Based on Wafer Topography
    Publication number: 20180315670
    Abstract: A wafer topography measurement system can be paired with a scanning electron microscope. A topography threshold can be applied to wafer topography data about the wafer, which was obtained with the wafer topography measurement system. A metrology sampling plan can be generated for the wafer. This metrology sampling plan can include locations in the wafer topography data above the topography threshold. The scanning electron microscope can scan the wafer using the metrology sampling plan and identify defects.
    Type: Application
    Filed: November 16, 2017
    Publication date: November 1, 2018
    Inventors: Arpit Yati, Shivam Agarwal, Jagdish Saraswatula, Andrew Cross
  • Shape based grouping
    Patent number: 9965848
    Abstract: Shape primitives are used for inspection of a semiconductor wafer or other workpiece. The shape primitives can define local topological and geometric properties of a design. One or more rules are applied to the shape primitives. The rules can indicate presence of a defect or the likelihood of a defect being present. A rule execution engine can search for an occurrence of the shape primitives covered by the at least one rule.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: May 8, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Saibal Banerjee, Ashok Kulkarni, Jagdish Saraswatula, Santosh Bhattacharyya
  • SHAPE BASED GROUPING
    Publication number: 20170186151
    Abstract: Shape primitives are used for inspection of a semiconductor wafer or other workpiece. The shape primitives can define local topological and geometric properties of a design. One or more rules are applied to the shape primitives. The rules can indicate presence of a defect or the likelihood of a defect being present. A rule execution engine can search for an occurrence of the shape primitives covered by the at least one rule.
    Type: Application
    Filed: November 18, 2016
    Publication date: June 29, 2017
    Inventors: Saibal Banerjee, Ashok Kulkarni, Jagdish Saraswatula, Santosh Bhattacharyya