Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.

Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.

Abstract: Embodiments herein may relate to an optoelectronic receiver that includes a photonic integrated circuit (PIC) coupled with a light source. Respective PIC sections of the PIC may include a photodiode and a junction capacitor. The optoelectronic receiver may further include an electronic integrated circuit (EIC) coupled with the PIC. Respective EIC sections of the EIC may be communicatively coupled to respective ones of the PIC sections. Other embodiments may be described and/or claimed.

Abstract: A switched capacitor is provided. The switched capacitor includes a pair of parallel component stacks. Each stack is connected to a common top node and a common bottom node. Each stack includes a BJT. Each stack further includes a first resistor in series with the BJT and having a first side connected to a collector of the BJT at an intermediate node in a same one of the stacks and a second side connected to the common top node. Each stack also includes a capacitor having a first side connected to the intermediate node and a second side for providing an impedance. Each stack additionally includes a second resistor having a first side connected to a base of the BJT to prevent base-current surge in the BJT and a second side connected to a switch base control signal that selectively turns the BJT on or off.

Abstract: Embodiments herein may relate to an optoelectronic receiver that includes a photonic integrated circuit (PIC) coupled with a light source. Respective PIC sections of the PIC may include a photodiode and a junction capacitor. The optoelectronic receiver may further include an electronic integrated circuit (EIC) coupled with the PIC. Respective EIC sections of the EIC may be communicatively coupled to respective ones of the PIC sections. Other embodiments may be described and/or claimed.

Abstract: A switched capacitor is provided. The switched capacitor includes a pair of parallel component stacks. Each stack is connected to a common top node and a common bottom node. Each stack includes a BJT. Each stack further includes a first resistor in series with the BJT and having a first side connected to a collector of the BJT at an intermediate node in a same one of the stacks and a second side connected to the common top node. Each stack also includes a capacitor having a first side connected to the intermediate node and a second side for providing an impedance. Each stack additionally includes a second resistor having a first side connected to a base of the BJT to prevent base-current surge in the BJT and a second side connected to a switch base control signal that selectively turns the BJT on or off.

Abstract: A switched capacitor is provided. The switched capacitor includes a pair of parallel component stacks. Each stack is connected to a common top node and a common bottom node. Each stack includes a BJT. Each stack further includes a first resistor in series with the BJT and having a first side connected to a collector of the BJT at an intermediate node in a same one of the stacks and a second side connected to the common top node. Each stack also includes a capacitor having a first side connected to the intermediate node and a second side for providing an impedance. Each stack additionally includes a second resistor having a first side connected to a base of the BJT to prevent base-current surge in the BJT and a second side connected to a switch base control signal that selectively turns the BJT on or off.

Abstract: A switched capacitor is provided. The switched capacitor includes a pair of parallel component stacks. Each stack is connected to a common top node and a common bottom node. Each stack includes a BJT. Each stack further includes a first resistor in series with the BJT and having a first side connected to a collector of the BJT at an intermediate node in a same one of the stacks and a second side connected to the common top node. Each stack also includes a capacitor having a first side connected to the intermediate node and a second side for providing an impedance. Each stack additionally includes a second resistor having a first side connected to a base of the BJT to prevent base-current surge in the BJT and a second side connected to a switch base control signal that selectively turns the BJT on or off.