Patents by Inventor Jai Bansal

Jai Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230336401
    Abstract: Techniques for determining an impact that a congested switch port is having on a network and for estimating a reason as to why the congested switch port is congested are disclosed. Configuration data and performance data from a network are obtained. Based on the configuration data, a shortest path between a storage port and a host port is identified. A particular switch port is also identified as a result of that port being congested. An impact as to how the switch port, due to its congestion in the particular shortest path, is impacting or is being impacted by other switch ports in the network is determined. An alert, which includes information indicating the impact, is triggered.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: Massarrah N. Tannous, Daniel Mckay, Erik P. Smith, Jai Bansal, Jean E. Pierre, Alan Rajapa
  • Publication number: 20070105731
    Abstract: A lubricating oil composition formulated with a viscosity index (VI) improver composition including a combination of an ethylene ?-olefin copolymer having no greater than 66 mass % of units derived from ethylene, and a linear diblock copolymer including at least one block derived primarily from a vinyl aromatic hydrocarbon monomer, and at least one block derived primarily from diene monomer.
    Type: Application
    Filed: November 4, 2005
    Publication date: May 10, 2007
    Inventors: Chin Chu, Rolfe Hartley, Stuart Briggs, Jacob Emert, Jai Bansal
  • Publication number: 20060015828
    Abstract: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.
    Type: Application
    Filed: June 7, 2005
    Publication date: January 19, 2006
    Applicant: BAE SYSTEMS Information and Electronic Systems Integration, Inc.
    Inventor: Jai Bansal
  • Publication number: 20050275432
    Abstract: An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the driver circuit in the active or high impedance modes. A feedback signal generated by the driver output and the driver enable signals controls an inverter circuit within the driver circuit to provide proper biasing conditions at the gate of the pull up transistor. This feed back provides fast switching times for the driver circuit and prevents gate oxide of all the transistors from being overstressed by the external high voltage signal.
    Type: Application
    Filed: April 15, 2005
    Publication date: December 15, 2005
    Applicant: BAE SYSTEMS Information and Electronic Systems Integration, Inc.
    Inventor: Jai Bansal
  • Publication number: 20050119138
    Abstract: Soot induced kinematic viscosity increase of lubricating oil compositions for diesel engines equipped with EGR systems can be ameliorated by selection of viscosity modifier, lubricating oil flow improvers, detergents and/or dispersants.
    Type: Application
    Filed: November 5, 2004
    Publication date: June 2, 2005
    Inventors: Andrew Ritchie, Jai Bansal, Jacob Emert, Glen Fetterman, Antonio Gutierrez, Matthew Irving, Christopher Locke, Michael Minotti
  • Publication number: 20050034095
    Abstract: A method for designing a cell-based ASIC device with multiple power supply voltages is disclosed. An ASIC chip image is made without applying power or ground buses to metal layer M1. All fast or high-power circuits are grouped together into high-power logic blocks and synthesized with high-power circuit macro libraries. All slow or low-power circuits are grouped together into low-power logic blocks and synthesized with low power circuit macro libraries. The associate power and ground buses are applied to metal layer M1 in each of the logic blocks. The logic blocks are placed on the ASIC so that different voltage groups are separated by at least one cell. The ASIC is then routed and tested before the mask is released.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 10, 2005
    Inventor: Jai Bansal