Patents by Inventor Jai Bharat Patel Gulabeela

Jai Bharat Patel Gulabeela has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Detection of memory access violation in simulations
    Patent number: 8838430
    Abstract: An apparatus and method for detecting memory access violations in simulations is disclosed herein. A detection tool is designed to automatically perform a violation check for each memory read or write operation simulated in a modeled system. The detection tool is capable of handling a modeled system including one or more memories and/or one or more processors.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: September 16, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tuay-Ling Kathy Lang, Neeti K. Bhatnagar, Jai Bharat Patel Gulabeela, George F. Frazier, Qizhang Chao