Abstract: A method of fabricating a semiconductor device includes forming a mask pattern over a semiconductor substrate to define a channel region. A portion of the semiconductor substrate is etched using the mask pattern as an etching mask to form a first pillar. A spacer is formed over a sidewall of the mask pattern and the first pillar. A portion of the semiconductor substrate exposed between the first pillars is etched using the spacer and the mask pattern as an etching mask to form a second pillar elongated from the first pillar. A portion of the second pillar is selectively etched to form a third pillar. The spacer and the mask pattern are removed. An impurity is implanted into an upper part of the first pillar and the semiconductor substrate between the third pillars to form a source/drain region. A surrounding gate is formed over an outside of the third pillar.

Abstract: A method for forming a DRAM cell wherein a semiconductor substrate having an n+ buried layer is etched to form a contact hole for storage electrode, and a MOS transistor of vertical structure having the n+ buried layer as an impurity region is formed therein is disclosed.

Abstract: A method for forming a DRAM cell wherein a semiconductor substrate having an n+ buried layer is etched to form a contact hole for storage electrode, and a MOS transistor of vertical structure having the n+ buried layer as an impurity region is formed therein is disclosed.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and formed at both sides of the gate electrode. In a transistor that is turned on/off depending on a voltage applied to the gate electrode, a region where the gate electrode and the source/drain overlap is maintained to have the same voltage by the auxiliary electrode by always applying a high voltage to the auxiliary electrode upon an on operation of the transistor even when the gate electrode becomes a zero (0) volt upon a refresh operation of a DRAM device. Therefore, the present invention can prevent generation of GIDL current. Further, even though the gate electrode is continuously turned on/off, the auxiliary electrode always maintains the same voltage between the gate electrode and the bit line.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and formed at both sides of the gate electrode. In a transistor that is turned on/off depending on a voltage applied to the gate electrode, a region where the gate electrode and the source/drain overlap is maintained to have the same voltage by the auxiliary electrode by always applying a high voltage to the auxiliary electrode upon an on operation of the transistor even when the gate electrode becomes a zero (0) volt upon a refresh operation of a DRAM device. Therefore, the present invention can prevent generation of GIDL current. Further, even though the gate electrode is continuously turned on/off, the auxiliary electrode always maintains the same voltage between the gate electrode and the bit line.

Abstract: A Metal Oxide Silicon Field Effect Transistor (MOSFET) and method includes a gate electrode pattern formed over a gate insulation layer on a semiconductor substrate. A pair of first impurity regions are respectively formed in an upper side surface of the substrate and adjacent to a side of the gate electrode pattern. A pair of first side wall spacers are respectively formed adjacent to a side wall of the gate electrode pattern, and a pair of air gaps are respectively formed between the gate electrode pattern and each of the side wall spacers. The MOSFET and method solve an increase problem of a fringing capacitor between a source and a gate electrode by forming an air gap along a side of the gate electrode. Further, a semiconductor chip area becomes decreased by forming a source and drain in a vertical structure. The source and drain formed of a side wall spacer further prevents a short channel effect from occurring. In addition, a cost reduction is achieved by adopting a self-alignment process.

Abstract: A method of manufacturing a field effect transistor (FET) includes the steps of: sequentially forming a conductive layer and a semiconductor layer on a first conductivity type substrate; patterning the semiconductor layer to form a gate electrode; implanting second conductivity type impurity ions at a low concentration into a surface of the substrate using the gate electrode as a mask, to thereby form low-concentration impurity regions in the substrate; forming and patterning an insulating layer on an overall surface of the substrate to form insulating side-wall spacers on side-walls of the gate electrode; and implanting second conductivity type FET impurity ions at a high concentration into a surface of the substrate using the gate electrode and insulating side-wall spacers as an etch-mask, to thereby form high-concentration impurity regions in the substrate.