Patents by Inventor Jai Dayal

Jai Dayal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240330188
    Abstract: Provided is a method for data processing, the method including generating, by a host, a work request in a queue in a shared memory, reading, by an accelerator circuit, the work request from the queue in the shared memory, the shared memory being a physical memory that is common to the host and the accelerator circuit, and performing, by the accelerator circuit, an operation on data in the shared memory based on the work request.
    Type: Application
    Filed: October 20, 2023
    Publication date: October 3, 2024
    Inventors: Jai Dayal, Douglas Joseph, Samantika Sury
  • Publication number: 20240330201
    Abstract: A system and method for address translation in a multi-node computing system. In some embodiments, the system includes a first node. The first node may include: a core; and a global address translation circuit, the core including: a core processing circuit; and a memory management unit configured to map local virtual addresses to global virtual addresses, the global address translation circuit being configured to map global virtual addresses to global physical addresses.
    Type: Application
    Filed: December 8, 2023
    Publication date: October 3, 2024
    Inventors: Alan Gara, Robert Wisniewski, Douglas Joseph, Samantika Sury, Jai Dayal, Rolf Riesen
  • Publication number: 20240311316
    Abstract: A computing node in a multi-node computing system includes a local memory, at least one processor, and an access library. The at least one processor runs an operating system that runs a distributed application in a virtual address space. The application includes a process that generates a first memory access request that includes a first virtual address. The access library is responsive to the first memory access request by: converting the first virtual address into a first physical address, accessing the local memory based on the first physical address including a first indication that the first memory access request is for the local memory, and accessing a global access tuple table based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the computing node.
    Type: Application
    Filed: September 14, 2023
    Publication date: September 19, 2024
    Inventors: David LOMBARD, Robert WISNIEWSKI, Douglas JOSEPH, Matthew WOLF, Jai DAYAL, James LOO, Andrew TAUFERNER, Rolf RIESEN
  • Publication number: 20240311308
    Abstract: Systems and methods for computing with multiple nodes. In some embodiments, the method includes: determining that a first data value in a cache is a global data value; setting a first flag to indicate that the first data value is a global data value; and selectively invalidating one or more portions of the cache, wherein the selective invalidating of the cache includes: determining, based on the first flag, that the first data value is a global data value; and based on the determining, invalidating the first data value.
    Type: Application
    Filed: December 8, 2023
    Publication date: September 19, 2024
    Inventors: Arun Francis RODRIGUES, Alan GARA, Douglas JOSEPH, Jai DAYAL, David LOMBARD, Manisha GAJBE, Andrew TAUFERNER, Casey THIELEN, Ping ZOU, Samantika SURY, Eric BORCH, Zaid MCKIE KRISBERG, Robert WISNIEWSKI
  • Publication number: 20240311289
    Abstract: A method to address memory in nodes of a distributed memory system includes partitioning the memory in each node into one or more memory blocks available for a global memory pool. The method also includes combining, in response to a request to address memory in the global memory pool, a global bit from a global page table with a physical address to generate a global virtual address. The global bit indicates whether the memory is local or remote. The method also includes translating, using global access tuple (GAT) tables, the global virtual address to a global physical address, and addressing a memory block in the global memory pool based on the global physical address.
    Type: Application
    Filed: March 1, 2024
    Publication date: September 19, 2024
    Inventors: David Lombard, Robert Wisniewski, Douglas Joseph, Matthew Wolf, Jai Dayal, James Loo, Andrew Thomas Tauferner, Rolf Riesen