Abstract: A system can maintain information indicative of prohibited computer operations, wherein the information is accessible to respective computing clusters of a group of computing clusters, and wherein the information is stored separately from the group of computing clusters. The system can obtain, by a service of a first computing cluster of the group of computing clusters, the information. The system can, in response to receiving, at the first computing cluster, a request to perform an operation on a first computer of the first computing cluster, in response to determining, based on the information, that the operation is prohibited, prevent the operation from occurring; and, in response to determining, based on the information, that the operation is not prohibited, permit the operation to occur.

Abstract: A high-endurance, computation-in-memory processor includes a plurality of memory computation modules (MCMs). Each of the MCMs comprise a plurality of memory arrays and a respective module controller to program the plurality of memory arrays to perform mathematical operations on a data set, as well as communicate with other of the MCMs to control a data flow between the MCMs. An inter-module interconnect transports operational data between the MCMs, and communicates with the MCMs to maintain queues storing the operational data during transport between the MCMs. A digital signal processor (DSP) transmits input data to the MCMs and retrieves processed data output by the MCMs.

Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. A digital controller interfaces with the crossbar arrays to direct write and read operations to the crossbar arrays.

Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. A digital controller interfaces with the crossbar arrays to direct write and read operations to the crossbar arrays.

Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. The analog crossbar array can be implemented in CMOS and memristors or a hybrid solution including a combination of CMOS and memristors.

Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. The analog crossbar array can be implemented in CMOS and memristors or a hybrid solution including a combination of CMOS and memristors.

Abstract: An image processor includes an analog correlator for providing correlation information among a pair of stereo images. The image processor includes an analog-to-digital converter (ADC), an analog correlator, and a digital processor. The ADC generates digital data corresponding to analog data of a plurality of images, the digital data being stored to a memory. The analog correlator circuit calculates correlation information among the plurality of images based on the analog data. The digital processor processes the digital data based on the correlation information to provide alignment of the images.

Abstract: Embodiments provide for dramatically improved interference resistance in advanced communications applications, where the frequency range can exceed 1 GHz. Such embodiments may be implemented using wideband technology to provide a wideband compressive sampling architecture that is capable of superior interference rejection through RF front end cancellation.

Abstract: Embodiments provide for dramatically improved interference resistance in advanced communications applications, where the frequency range can exceed 1 GHz. Such embodiments may be implemented using wideband technology to provide a wideband compressive sampling architecture that is capable of superior interference rejection through RF front end cancellation.