Patents by Inventor Jai Heon CHO

Jai Heon CHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-chip detector appratus
    Patent number: 10930620
    Abstract: The present invention relates to a multi-chip detector apparatus composed of multiple single detectors. An embodiment of the invention provides a multi-chip detector apparatus having a multiple number of single chips arranged in inter-chip connection on a substrate, where the multi-chip detector apparatus includes: a first single chip that has a multiple number of single detectors formed in m rows and n columns; a second single chip that is positioned at either a left side or a right side of the first single chip and is connected row-wise with the first single chip; and a third single chip that is positioned at either an upper side or a lower side of the first single chip and is connected column-wise with the first single chip, and where the second single chip and the third single chip also have multiple numbers of single detectors formed in m rows and n columns.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: February 23, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jae-Sung Rieh, Ki Ryong Song, Jai Heon Cho, DoYoon Kim
  • MULTI-CHIP DETECTOR APPRATUS
    Publication number: 20200043898
    Abstract: The present invention relates to a multi-chip detector apparatus composed of multiple single detectors. An embodiment of the invention provides a multi-chip detector apparatus having a multiple number of single chips arranged in inter-chip connection on a substrate, where the multi-chip detector apparatus includes: a first single chip that has a multiple number of single detectors formed in m rows and n columns; a second single chip that is positioned at either a left side or a right side of the first single chip and is connected row-wise with the first single chip; and a third single chip that is positioned at either an upper side or a lower side of the first single chip and is connected column-wise with the first single chip, and where the second single chip and the third single chip also have multiple numbers of single detectors formed in m rows and n columns.
    Type: Application
    Filed: July 9, 2019
    Publication date: February 6, 2020
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Jae-Sung RIEH, Ki Ryong SONG, Jai Heon CHO, DoYoon KIM