Patents by Inventor Jai-hoon Sim

Jai-hoon Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9231066
    Abstract: A vertical-channel semiconductor device includes an active pillar including a channel region, a gate located at a sidewall of the active pillar, a buried bit-line formed below the active pillar, and an insulation film formed below the buried bit-line. Some parts of the buried bit-line are replaced with an insulation film, such that a bit-line junction leakage is prevented.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: January 5, 2016
    Assignee: SK HYNIX INC.
    Inventors: Seung Hwan Kim, Jai Hoon Sim
  • Patent number: 9196617
    Abstract: A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 24, 2015
    Assignee: SK HYNIX INC.
    Inventors: Seung Hwan Kim, Jai Hoon Sim
  • Publication number: 20150008495
    Abstract: A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 8, 2015
    Inventors: Seung Hwan KIM, Jai Hoon SIM
  • Publication number: 20140353745
    Abstract: A vertical-channel semiconductor device includes an active pillar including a channel region, a gate located at a sidewall of the active pillar, a buried bit-line formed below the active pillar, and an insulation film formed below the buried bit-line. Some parts of the buried bit-line are replaced with an insulation film, such that a bit-line junction leakage is prevented.
    Type: Application
    Filed: March 11, 2014
    Publication date: December 4, 2014
    Applicant: SK HYNIX INC.
    Inventors: Seung Hwan KIM, Jai Hoon SIM
  • Patent number: 8872259
    Abstract: A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: October 28, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Hwan Kim, Jai Hoon Sim
  • Publication number: 20140021537
    Abstract: A semiconductor device and a method for forming the same includes a pillar formed over a semiconductor substrate, a buried bit line formed below the semiconductor substrate, a vertical gate formed over a sidewall of the pillar, an insulation film pattern formed to expose one side of the vertical gate disposed between the pillars, and a word line coupled to the exposed vertical gate. The vertical gate is formed to cover a portion of a sidewall of the pillar with a metal material, a word line overlaps with some parts of the vertical gate, and some parts of the pillar are shifted to be coupled to the vertical gate.
    Type: Application
    Filed: March 18, 2013
    Publication date: January 23, 2014
    Applicant: SK HYNIX INC.
    Inventors: Seung Hwan KIM, Jai Hoon SIM
  • Patent number: 8467220
    Abstract: The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word line, and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor. A gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells. An interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: June 18, 2013
    Inventor: Jai Hoon Sim
  • Publication number: 20130105872
    Abstract: A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.
    Type: Application
    Filed: April 12, 2012
    Publication date: May 2, 2013
    Applicant: Hynix Semiconductor Inc.
    Inventors: Seung Hwan KIM, Jai Hoon Sim
  • Publication number: 20120236620
    Abstract: The present invention relates to a nonvolatile memory device and a manufacturing method thereof, the device comprising a plurality of word lines; a plurality of bit lines perpendicular to the word lines; and a plurality of memory cells including a transistor with a source connected to a source line, a gate, and a drain connected to a memory element, with the other end of the memory element connected to the bit lines. Between memory cells adjacent along a bit line, a gate terminal in a groove between the memory cells connects the gates in the memory cells to a word line. Memory cells adjacent along a word line are connected to one bit line contact point, and memory cells sharing a gate terminal are connected to different bit lines. Bit lines are disposed at the upper portion and source lines at the lower end of the memory cell.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 20, 2012
    Inventor: Jai-Hoon Sim
  • Publication number: 20120134195
    Abstract: The present invention relates to a memory device having 4F2 size cells and a method for fabricating the same. The memory device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other, and plural memory cells having a transistor that fills a groove between two adjoining memory cells in a direction of the bit lines. A side wall between the two adjoining memory cells is simultaneously covered by an insulating film formed between the gate terminal and the two memory cells. The gate terminal is connected electrically to a word line, drain terminals of two adjoining memory cells are connected electrically to a bit line, and the gate and drain terminals are alternately arranged. One of the plural memory cells is buried in the substrate, and is electrically connected with a substrate or a well formed in the substrate.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 31, 2012
    Inventor: Jai-Hoon Sim
  • Patent number: 8084321
    Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: December 27, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jai-Hoon Sim
  • Publication number: 20110230023
    Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.
    Type: Application
    Filed: June 2, 2011
    Publication date: September 22, 2011
    Inventor: Jai-Hoon SIM
  • Publication number: 20110170336
    Abstract: The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word line, and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor. A gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells. An interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size.
    Type: Application
    Filed: August 13, 2010
    Publication date: July 14, 2011
    Inventor: Jai Hoon Sim
  • Patent number: 7977726
    Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 12, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jai-Hoon Sim
  • Patent number: 7541241
    Abstract: A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: June 2, 2009
    Assignee: Promos Technologies, Inc.
    Inventors: Jai Hoon Sim, Jih Wen Chou
  • Publication number: 20090057741
    Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 5, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jai-Hoon Sim
  • Publication number: 20080057660
    Abstract: A semiconductor device using a recessed step gate. An embodiment comprises a recessed region in a portion of the substrate, a transistor with one source/drain region located within the recessed region and one source/drain region located out of the recessed region, a storage device connected to the source/drain located out of the recessed region, and a bit line connected to the source/drain located within the recessed region.
    Type: Application
    Filed: August 29, 2006
    Publication date: March 6, 2008
    Inventors: Kuo-Chi Tu, Jai-Hoon Sim, Chun-Yao Chen
  • Patent number: 6440793
    Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Heon Lee, Jack A. Mandelman, Carl J. Radens, Jai-Hoon Sim
  • Patent number: 6441422
    Abstract: An ultra-scalable hybrid memory cell having a low junction leakage and a process of fabricating the same are provided. The ultra-scalable hybrid memory cell contains a conductive connection to the body region therefore avoiding isolation of the P-well due to cut-off by the buried strap outdiffusion region. The ultra-scalable hybrid memory cell avoids the above by using a shallower than normal isolation region that allows the P-well to remain connected to the body of the memory cell.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jack A. Mandelman, Ramachandra Divakaruni, Carl J. Radens, Jai-hoon Sim
  • Publication number: 20020090780
    Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
    Type: Application
    Filed: January 10, 2001
    Publication date: July 11, 2002
    Inventors: Ramachandra Divakaruni, Heon Lee, Jack A. Mandelman, Carl J. Radens, Jai-Hoon Sim