Patents by Inventor Jai-kyeong Shinn

Jai-kyeong Shinn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor multi-chip package including two semiconductor memory chips having different memory densities
    Patent number: 7486532
    Abstract: A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: February 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-jib Han, Jai-kyeong Shinn
  • Semiconductor multi-chip package including two semiconductor memory chips having different memory densities
    Publication number: 20070045827
    Abstract: A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.
    Type: Application
    Filed: August 23, 2006
    Publication date: March 1, 2007
    Inventors: Sang-jib Han, Jai-kyeong Shinn