Patents by Inventor Jai-Ming Lin
Jai-Ming Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11048850Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.Type: GrantFiled: November 6, 2019Date of Patent: June 29, 2021Assignees: NCKU Research and Development Foundation, Himax Technologies LimitedInventors: Jai-Ming Lin, Jhih-Sheng Syu, Bo-Yuan Huang
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Patent number: 10628627Abstract: An embodiment of a thermal estimation device including a temperature model generator, a temperature gradient calculator, and a thermal sensing analyzer is disclosed. The temperature model generator generates a temperature model based on an initial power consumption, an initial area and an initial coordination of a circuit module. The temperature gradient calculator substitutes at least one of a testing area, a testing power or a testing coordinate of the circuit module into the temperature model for correspondingly estimating an temperature estimation function. The thermal sensing analyzer differentiates the temperature estimation function. When an absolute value of a differential result of the temperature estimation function resulted from a constant is closest to zero or is zero, outputting the constant as an optimized parameter.Type: GrantFiled: December 28, 2017Date of Patent: April 21, 2020Assignee: Industrial Technology Research InstituteInventors: Yeong-Jar Chang, Ya-Ting Shyu, Juin-Ming Lu, Yao-Hua Chen, Yen-Fu Chang, Jai-Ming Lin
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Publication number: 20200074037Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Jai-Ming Lin, Jhih-Sheng Syu, Bo-Yuan Huang
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Patent number: 10579765Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.Type: GrantFiled: July 26, 2018Date of Patent: March 3, 2020Assignees: NCKU Research and Development Foundation, Himax Technologies LimitedInventors: Jai-Ming Lin, Jhih-Sheng Syu, Bo-Yuan Huang
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Publication number: 20200034506Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.Type: ApplicationFiled: July 26, 2018Publication date: January 30, 2020Inventors: Jai-Ming Lin, Jhih-Sheng Syu, Bo-Yuan Huang
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Publication number: 20190147135Abstract: An embodiment of a thermal estimation device including a temperature model generator, a temperature gradient calculator, and a thermal sensing analyzer is disclosed. The temperature model generator generates a temperature model based on an initial power consumption, an initial area and an initial coordination of a circuit module. The temperature gradient calculator substitutes at least one of a testing area, a testing power or a testing coordinate of the circuit module into the temperature model for correspondingly estimating an temperature estimation function. The thermal sensing analyzer differentiates the temperature estimation function. When an absolute value of a differential result of the temperature estimation function resulted from a constant is closest to zero or is zero, outputting the constant as an optimized parameter.Type: ApplicationFiled: December 28, 2017Publication date: May 16, 2019Inventors: Yeong-Jar CHANG, Ya-Ting Shyu, Juin-Ming Lu, Yao-Hua Chen, Yen-Fu Chang, Jai-Ming Lin
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Patent number: 7383528Abstract: A method of the invention is used for checking a wire layout causing high wire resistance. The method includes the steps of: selecting a first metal layer, a second metal layer and a third metal layer, wherein each of the first and third metal layer includes a power wire for transmitting power, and the second metal layer is adjacent to the first and third metal layers; selecting one region in the second metal layer, wherein the first and the third metal layers have the power wires at positions corresponding to the region and the second metal layer has no wire at the region; and disposing a conductive metal layer coupled to the first and third metal layer in the region for lowering the equivalent wire resistance.Type: GrantFiled: August 24, 2004Date of Patent: June 3, 2008Assignee: Realtek Semiconductor Corp.Inventors: Jai-Ming Lin, Chao-Cheng Lee
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Patent number: 7257787Abstract: A method of the invention is used for checking the via density between two adjacent layers of an IC layout. The method includes selecting a first metal layer and a second metal layer, wherein the first metal layer is adjacent to the second one, each of the metal layers has at least a wire, and the metal layers are coupled to each other through at least a first via; calculating the cross-sectional area of the first via and the overlapping area of the overlapped part of the wires in the first and the second metal layers; and disposing at least a second via in the overlapped part to couple the first and the second metal layers if the ratio of the cross-sectional area to the overlapping area is smaller than a predetermined ratio value.Type: GrantFiled: August 24, 2004Date of Patent: August 14, 2007Assignee: Realtek Semiconductor Corp.Inventors: Jai-Ming Lin, Chao-Cheng Lee
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Patent number: 7134108Abstract: A method for checking an IC layout is used for checking the wire line width in the circuit layout. The IC includes at least a first metal layer having at least a wire, and the wire has a plurality of wire segments. The method includes the steps of checking the width of each wire segment, wherein if at least a narrow wire segment has a width smaller than a predetermined width, the narrow wire segment is removed; if there is at least a non-coupling wire segment not coupled to a voltage source in the remained wire segments, outputting the non-coupling wire and disposing a coupling wire to couple the non-coupling wire segment and the voltage source.Type: GrantFiled: August 24, 2004Date of Patent: November 7, 2006Assignee: Realtek Semiconductor Corp.Inventors: Jai-Ming Lin, Chao-Cheng Lee
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Publication number: 20050055653Abstract: A method of the invention is used for checking a wire layout causing high wire resistance. The method includes the steps of: selecting a first metal layer, a second metal layer and a third metal layer, wherein each of the first and third metal layer includes a power wire for transmitting power, and the second metal layer is adjacent to the first and third metal layers; selecting one region in the second metal layer, wherein the first and the third metal layers have the power wires at positions corresponding to the region and the second metal layer has no wire at the region; and disposing a conductive metal layer coupled to the first and third metal layer in the region for lowering the equivalent wire resistance.Type: ApplicationFiled: August 24, 2004Publication date: March 10, 2005Inventors: Jai-Ming Lin, Chao-Cheng Lee
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Publication number: 20050055654Abstract: A method of the invention is used for checking the via density between two adjacent layers of an IC layout. The method includes selecting a first metal layer and a second metal layer, wherein the first metal layer is adjacent to the second one, each of the metal layers has at least a wire, and the metal layers are coupled to each other through at least a first via; calculating the cross-sectional area of the first via and the overlapping area of the overlapped part of the wires in the first and the second metal layers; and disposing at least a second via in the overlapped part to couple the first and the second metal layers if the ratio of the cross-sectional area to the overlapping area is smaller than a predetermined ratio value.Type: ApplicationFiled: August 24, 2004Publication date: March 10, 2005Inventors: Jai-Ming Lin, Chao-Cheng Lee
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Publication number: 20050055652Abstract: A method for checking an IC layout is used for checking the wire line width in the circuit layout. The IC includes at least a first metal layer having at least a wire, and the wire has a plurality of wire segments. The method includes the steps of checking the width of each wire segment, wherein if at least a narrow wire segment has a width smaller than a predetermined width, the narrow wire segment is removed; if there is at least a non-coupling wire segment not coupled to a voltage source in the remained wire segments, outputting the non-coupling wire and disposing a coupling wire to couple the non-coupling wire segment and the voltage source.Type: ApplicationFiled: August 24, 2004Publication date: March 10, 2005Inventors: Jai-Ming Lin, Chao-Cheng Lee