Patents by Inventor Jai N. Subrahmanyam
Jai N. Subrahmanyam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140258801Abstract: Systems and methods are provided for mitigating interference in a wireless network to facilitate network performance. In an aspect, a method for transmitting wireless data packets is provided. The method includes receiving data packets from a wireless distribution network. The data packets are analyzed to determine if a subset of the data packets are to be suppressed in view of transmitter signal conditions and substituting null packets for the subset of data packets if the subset of data packets are determined to be suppressed.Type: ApplicationFiled: May 20, 2014Publication date: September 11, 2014Applicant: QUALCOMM IncorporatedInventors: Gordon Kent WALKER, Bruce COLLINS, Christopher R. WINGERT, Jai N. SUBRAHMANYAM, Michael Mao WANG
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Patent number: 8792865Abstract: Systems and methods are provided for mitigating interference in a wireless network to facilitate network performance. In an aspect, a method for transmitting wireless data packets is provided. The method includes receiving data packets from a wireless distribution network. The data packets are analyzed to determine if a subset of the data packets are to be suppressed in view of transmitter signal conditions and substituting null packets for the subset of data packets if the subset of data packets are determined to be suppressed.Type: GrantFiled: December 18, 2006Date of Patent: July 29, 2014Assignee: QUALCOMM IncorporatedInventors: Gordon Kent Walker, Bruce Collins, Christopher R. Wingert, Jai N. Subrahmanyam, Michael Mao Wang
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Patent number: 8612504Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.Type: GrantFiled: December 18, 2006Date of Patent: December 17, 2013Assignee: QUALCOMM IncorporatedInventors: Jai N. Subrahmanyam, Chinnappa K. Ganapathy, Durk L. Van Veen, Jinxia Bai, Kevin S. Cousineau, Seokyong Oh
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Patent number: 8543629Abstract: Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.Type: GrantFiled: December 18, 2006Date of Patent: September 24, 2013Assignee: QUALCOMM IncorporatedInventors: Jai N. Subrahmanyam, Chinnappa K. Ganapathy, Durk L. Van Veen, Jinxia Bai, Kevin S. Cousineau, Seokyong Oh
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Patent number: 7693124Abstract: In an OFDM system, multiple (M) interlaces are defined for M non-overlapping sets of frequency subbands, and M slots with fixed indices are also defined. Data streams and pilot are mapped to slots, which are in turn mapped to interlaces based on a slot-to-interlace mapping scheme that can achieve frequency diversity and good performance for all slots. At a transmitter, a slot-to-interlace converter maps the slots to the interlaces. The slot-to-interlace converter includes multiple multiplexers and a control unit. The multiplexers map the M slots to the M interlaces based on the slot-to-interlace mapping scheme. The control unit generates at least one control signal for the multiplexers. The multiplexers may be arranged and controlled in various manners depending on the slot-to-interlace mapping scheme. At a receiver, a complementary interlace-to-slot converter maps the interlaces to the slots.Type: GrantFiled: May 18, 2005Date of Patent: April 6, 2010Assignee: QUALCOMM IncorporatedInventors: Jai N. Subrahmanyam, Kevin Stuart Cousineau, Michael Mao Wang
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Patent number: 7613256Abstract: A multimedia distribution system is disclosed. The distribution system includes a transmitter unit that distributes content from a content provider to one or more wireless subscriber units. The transmitter unit includes a decoder configured to determine whether a plurality of incoming packets include one or more erasures, a transmitter configured to transmit the packets to a receiving unit, and an error detection code generator configured to generate an error detection code for each of the packets transmitted to the receiver unit, the error detection code being modified for each of the erased packets so that the receiver unit will be able to identify the erased packets.Type: GrantFiled: April 4, 2006Date of Patent: November 3, 2009Assignee: QUALCOMM IncorporatedInventors: Durk L. van Veen, Jai N. Subrahmanyam, Jinxia Bai, Murali Ramaswamy Chari
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Publication number: 20080159278Abstract: Multiplexer to transmitter interface protocol. A method for a data interface protocol is provided that includes receiving a first packet stream having at least one overhead information symbol (OIS) group and at least one multicast logical channel (MLC) group, and mapping each OIS group to an OIS descriptor packet and at least one OIS payload packet. The method also includes mapping each MLC group to an MLC descriptor packet and at least one MLC payload packet, and outputting the OIS descriptor, OIS payload, MLC descriptor, and MLC payload packets in a second packet stream. An apparatus includes input logic to receive the first packet stream, processing logic to map each OIS group to an OIS descriptor packet an OIS payload packet, and each MLC group to an MLC descriptor packet and an MLC payload packet, and output logic to output the mapped packets in a second packet stream.Type: ApplicationFiled: April 24, 2007Publication date: July 3, 2008Inventors: Sajith Balraj, Kenton A. Younkin, Bruce Collins, Robert Riley, Ben A. Saidi, Jai N. Subrahmanyam
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Publication number: 20080040413Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.Type: ApplicationFiled: December 18, 2006Publication date: February 14, 2008Applicant: QUALCOMM INCORPORATEDInventors: Jai N. Subrahmanyam, Chinnappa K. Ganapathy, Durk L. van Veen, Jinxia Bai, Kevin S. Cousineau, Seokyong Oh
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Publication number: 20080040412Abstract: Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.Type: ApplicationFiled: December 18, 2006Publication date: February 14, 2008Applicant: QUALCOMM INCORPORATEDInventors: Jai N. Subrahmanyam, Chinnappa K. Ganapathy, Durk L. van Veen, Jinxia Bai, Kevin S. Cousineau, Seokyong Oh
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Patent number: 7330327Abstract: A method of servo writing a disk for use in a disk drive is disclosed by writing discontinuous spiral tracks on the disk to protect against overheating the head and/or preamp circuitry. A write clock is synchronized to the rotation of the disk, and a plurality of discontinuous spiral tracks are written on the disk. Each discontinuous spiral track is written at a predetermined circular location determined from the write clock, and each discontinuous spiral track comprises a plurality of segments separated by gaps. Each segment comprises a high frequency signal interrupted at a predetermined interval by a sync mark.Type: GrantFiled: June 23, 2004Date of Patent: February 12, 2008Assignee: Western Digital Technologies, Inc.Inventors: Jack M. Chue, Siri S. Weerasooriya, Jai N. Subrahmanyam
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Publication number: 20080002611Abstract: Systems and methods are provided for mitigating interference in a wireless network to facilitate network performance. In an aspect, a method for transmitting wireless data packets is provided. The method includes receiving data packets from a wireless distribution network. The data packets are analyzed to determine if a subset of the data packets are to be suppressed in view of transmitter signal conditions and substituting null packets for the subset of data packets if the subset of data packets are determined to be suppressed.Type: ApplicationFiled: December 18, 2006Publication date: January 3, 2008Applicant: QUALCOMM INCORPORATEDInventors: Gordon Kent Walker, Bruce Collins, Christopher R. Wingert, Jai N. Subrahmanyam, Michael Mao Wang
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Patent number: 7184230Abstract: A system and method for processing track identifier errors to mitigate head instability in data storage devices is disclosed. The system and method includes computing a track id differential between an expected track id and a received track id, encoding the expected track id and the received track id, initiating a first action if the track id differential exceeds a pre-determined threshold and the encoded expected track id varies from the encoded received track id by a pre-configured number of bits, and initiating a second action if the track id differential does not exceed the pre-determined threshold or the encoded expected track id does not vary from the encoded received track id by a pre-configured number of bits.Type: GrantFiled: June 1, 2002Date of Patent: February 27, 2007Assignee: Western Digital Technologies, Inc.Inventors: Jack M. Chue, Jai N. Subrahmanyam, Russ A. Quisenberry
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Patent number: 7180703Abstract: A disk drive is disclosed comprising a disk, a head actuated over the disk, and a spindle motor for rotating the disk. The spindle motor comprises a rotating component, a stationary component, and a first and second bearing assembly disposed between the rotating component and stationary component for rotating the rotating component about the stationary component, wherein the disk is attached to the rotating component. The bearing assemblies comprise a stationary component surface and a rotating component surface having a lubricant disposed there between. The first bearing assembly employs an anionic lubricant such that a first voltage forms between the stationary component surface and the rotating component surface when the rotating component rotates about the stationary component.Type: GrantFiled: May 15, 2004Date of Patent: February 20, 2007Assignee: Western Digital Technologies, Inc.Inventors: Jai N. Subrahmanyam, Jack M. Chue
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Patent number: 7099117Abstract: A head stack assembly includes a flex cable assembly. The head stack assembly further includes an actuator arm and a load beam coupled to the actuator arm. The head stack assembly further includes a trace suspension assembly backing layer coupled to the load beam and including a gimbal. The head stack assembly further includes a dielectric layer disposed upon the trace suspension assembly backing layer. The head stack assembly further includes a slider supported by the gimbal. The head stack assembly further includes a ground trace disposed upon the dielectric layer with the dielectric layer between the ground trace and the trace suspension assembly backing layer. The ground trace extends along the actuator arm and is electrically connected to the slider and the flex cable assembly for grounding the slider to the flex cable assembly.Type: GrantFiled: September 30, 2003Date of Patent: August 29, 2006Assignee: Western Digital Technologies, Inc.Inventors: Jai N. Subrahmanyam, Gopalakrishna Kote, Kathy X. Tang, Loi D. Pham, Jack M. Chue
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Patent number: 7099095Abstract: The present invention may be embodied in a disk drive comprising a rotating magnetic media having tracks identified by binary codewords, and in a related method. Each track codeword for a particular track within a contiguous band of tracks differs from a track codeword for an adjacent track within the contiguous band of tracks by a defined number of bits, and differs from a track codeword for a nonadjacent track within the contiguous band of tracks by at least the defined number of bits. The defined number N of bits is greater than four such that at least two bit errors may be corrected when reading a track codeword.Type: GrantFiled: January 30, 2004Date of Patent: August 29, 2006Assignee: Western Digital Technologies, Inc.Inventors: Jai N. Subrahmanyam, Jack M. Chue
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Patent number: 7050249Abstract: A system and method for processing track identification data in a disk drive having concentric tracks each having a track identification field (TIF) stored in embedded servo sectors, the TIF includes a band segment identifying a group of tracks, and an index segment identifying a single track of the group of tracks. The system and method include reading a servo sector to obtain the TIF, parsing the TIF to obtain the band segment, comparing the obtained band segment to an expected band segment to obtain a band segment differential (BSD), initiating an action if the BSD exceeds a pre-determined threshold and varies from the expected band segment by a predetermined number of bits, initiating another action if the BSD exceeds the predetermined threshold and does not vary from the expected band segment by the predetermined number of bits. The process is then applied to the index segments of the band segment.Type: GrantFiled: December 24, 2002Date of Patent: May 23, 2006Assignee: Western Digital Technologies, Inc.Inventors: Jack M. Chue, Jai N. Subrahmanyam
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Patent number: 7027264Abstract: According to an aspect of the present invention, there is provided a slider for a disk drive. The slider includes a slider body including a slider body outer surface. The slider further includes an inductive write head including main and return poles. The slider further includes a slider ground pad disposed at the slider body outer surface. The slider ground pad is disposed in electrical communication with the main and return poles for electrically grounding the main and return poles.Type: GrantFiled: October 31, 2003Date of Patent: April 11, 2006Assignee: Western Digital Technologies, Inc.Inventors: Jai N. Subrahmanyam, Gopalakrishna Kote, Kathy X. Tang, Loi D Pham, Jack M. Chue
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Patent number: 7027256Abstract: A magnetic disk drive having a reduction in repeatable runout (RRO) effects is disclosed. The disk drive has a head disk assembly (HDA) and a sampled servo controller. The HDA includes a rotating magnetic disk, an actuator, and a transducer head. The magnetic disk has a plurality of embedded servo sectors for storing servo information including repeatable runout (RRO) cancellation values and RRO cancellation value error correction code (ECC) data at a servo data rate. The RRO cancellation value ECC data is only for detecting and correcting errors in the RRO cancellation values. In between the embedded servo sectors are data sectors for storing user data at a user data rate that is different from the servo data rate. The actuator positions the transducer head in response to a control effort signal generated by the sampled servo controller based on the servo information.Type: GrantFiled: February 28, 2003Date of Patent: April 11, 2006Assignee: Western Digital Technologies, Inc.Inventors: Jai N. Subrahmanyam, Jack M. Chue, Robert J. McNab
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Patent number: 7006330Abstract: A head stack assembly includes an actuator including an actuator arm, a load beam coupled to the actuator arm, and a gimbal coupled to the load beam. The gimbal is formed of an electrically conductive material. The head stack assembly further includes a dielectric layer disposed upon the gimbal. The head stack assembly further includes a slider supported by the gimbal. The head stack assembly further includes slider conductive pads disposed upon the dielectric layer with the dielectric layer interposed between the slider conductive pads and the gimbal. The slider conductive pads are electrically connected to the slider. The head stack assembly further includes a ground conductive pad disposed upon the dielectric layer with the dielectric layer interposed between the ground conductive pad and the gimbal. The ground conductive pad is electrically connected to the slider and the gimbal for electrically grounding the slider.Type: GrantFiled: March 10, 2003Date of Patent: February 28, 2006Assignee: Western Digital Technologies, Inc.Inventors: Jai N. Subrahmanyam, Darrell D. Palmer
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Patent number: 7006331Abstract: A head gimbal assembly for a disk drive. The head gimbal assembly includes a trace suspension assembly backing layer including a gimbal. The trace suspension assembly backing layer is formed of a conductive material having a first oxidation rate. The head gimbal assembly further includes a gimbal conductive layer disposed upon the gimbal and formed of a conductive material having a second oxidation rate lower than the first oxidation rate. The head gimbal assembly further includes a slider supported by the gimbal. The head gimbal assembly further includes a conductive compound disposed between the gimbal conductive layer and the slider for electrically grounding the slider to the trace suspension assembly backing layer.Type: GrantFiled: September 30, 2003Date of Patent: February 28, 2006Assignee: Western Digital Technologies, Inc.Inventors: Jai N. Subrahmanyam, Pierre C. Humbert