Patents by Inventor Jai P. Bansal
Jai P. Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8975920Abstract: A multi-function programmable transceiver is described. The transceiver includes a driver circuit and a receiver circuit, which allows an Application Specific Integrated Circuit (ASIC) device to drive and receive data from other ASIC devices. Both the driver and receiver circuits share a common input/output (I/O) pin. The driver circuit can be programmed to provide one of the several driver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS. Other functional features of the transceiver that can be programmed are driving strengths or output impedance, output power supply voltage, single ended or differential mode of HSTL/SSTL transceivers, and class 1 or class 2 operations for SSTL/HSTL transceivers. The receiver circuit can also be programmed to provide one of the several receiver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS.Type: GrantFiled: August 13, 2012Date of Patent: March 10, 2015Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Jai P. Bansal
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Publication number: 20130207689Abstract: A multi-function programmable transceiver is described. The transceiver includes a driver circuit and a receiver circuit, which allows an Application Specific Integrated Circuit (ASIC) device to drive and receive data from other ASIC devices. Both the driver and receiver circuits share a common input/output (I/O) pin. The driver circuit can be programmed to provide one of the several driver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS. Other functional features of the transceiver that can be programmed are driving strengths or output impedance, output power supply voltage, single ended or differential mode of HSTL/SSTL transceivers, and class 1 or class 2 operations for SSTL/HSTL transceivers. The receiver circuit can also be programmed to provide one of the several receiver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS.Type: ApplicationFiled: August 13, 2012Publication date: August 15, 2013Applicant: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.Inventor: JAI P. BANSAL
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Patent number: 7895559Abstract: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.Type: GrantFiled: July 17, 2008Date of Patent: February 22, 2011Assignee: BAE System Information and Electric Systems Integration Inc.Inventor: Jai P. Bansal
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Publication number: 20080282216Abstract: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.Type: ApplicationFiled: July 17, 2008Publication date: November 13, 2008Inventor: Jai P. Bansal
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Patent number: 7418692Abstract: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.Type: GrantFiled: June 7, 2005Date of Patent: August 26, 2008Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Jai P. Bansal
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Patent number: 7239177Abstract: An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the driver circuit in the active or high impedance modes. A feedback signal generated by the driver output and the driver enable signals controls an inverter circuit within the driver circuit to provide proper biasing conditions at the gate of the pull up transistor. This feed back provides fast switching times for the driver circuit and prevents gate oxide of all the transistors from being overstressed by the external high voltage signal.Type: GrantFiled: April 15, 2005Date of Patent: July 3, 2007Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Jai P. Bansal
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Patent number: 6944843Abstract: A method for designing a cell-based ASIC device with multiple power supply voltages is disclosed. An ASIC chip image is made without applying power or ground buses to metal layer M1. All fast or high-power circuits are grouped together into high-power logic blocks and synthesized with high-power circuit macro libraries. All slow or low-power circuits are grouped together into low-power logic blocks and synthesized with low power circuit macro libraries. The associate power and ground buses are applied to metal layer M1 in each of the logic blocks. The logic blocks are placed on the ASIC so that different voltage groups are separated by at least one cell. The ASIC is then routed and tested before the mask is released.Type: GrantFiled: August 5, 2003Date of Patent: September 13, 2005Assignee: BAE Systems, Information and Electronic Systems Integration, Inc.Inventor: Jai P. Bansal
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Patent number: 6765245Abstract: A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly.Type: GrantFiled: December 19, 2002Date of Patent: July 20, 2004Assignee: Bae Systems Information and Electronic Systems Integration Inc.Inventor: Jai P. Bansal
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Publication number: 20030178648Abstract: A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly.Type: ApplicationFiled: December 19, 2002Publication date: September 25, 2003Inventor: Jai P. Bansal
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Patent number: 5858817Abstract: A method of making gate array ASIC components from a master slice wafer having a first conducting layer containing logic elements, a second conducting layer containing first electrically conducting elements extending in a first direction, and a third conducting layer comprises interconnecting at least some of the logic elements to one another with a single masking process step by defining, on the third conducting layer, second conducting elements connected to the first electrically conducting elements to define connections between the logic elements.Type: GrantFiled: October 10, 1996Date of Patent: January 12, 1999Assignee: Lockheed Martin CorporationInventor: Jai P. Bansal
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Patent number: 5504703Abstract: SEU immunity is provided in a cross-coupled CMOS latch circuit by inserting a pair of series connected invertors between the drain node of one CMOS invertor and the gate node of the other CMOS invertor and a pair of series connected invertors between the drain node of the other CMOS invertor and the gate node of the one CMOS invertor. The invertor pairs delay the propagation of a change in voltage induced by an energetic ion strike at the off drain of one invertor to the gates of the transistors making up the other cross coupled invertor. The invertor connected to the gates of the transistors affected by the ion strike help in restoring the circuit to its original state.Type: GrantFiled: February 1, 1995Date of Patent: April 2, 1996Assignee: Loral Federal Systems CompanyInventor: Jai P. Bansal
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Patent number: 4555721Abstract: A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.Type: GrantFiled: November 4, 1983Date of Patent: November 26, 1985Assignee: International Business Machines CorporationInventors: Jai P. Bansal, Claude L. Bertin, Ronald R. Troutman
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Patent number: 4467518Abstract: A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.Type: GrantFiled: February 7, 1983Date of Patent: August 28, 1984Assignee: IBM CorporationInventors: Jai P. Bansal, Claude L. Bertin, Ronald R. Troutman
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Patent number: 4418401Abstract: An asymmetric RAM cell is disclosed which will have a predictable initial storage state when pulsed drain voltage is turned on and yet after the initial turn-on interval, will operate in a symmetric fashion storing either binary ones or zeros. Thus, an initial prestored set of information can be permanently provided in a memory array made up of such cells, by orienting each individual cell at the time of manufacture so as to selectively represent either a binary one or zero. This is illustrated in the FIGURE where the upper cell has a first state by virtue of its orientation and the lower cell has a second, opposite state by virtue of its relative opposite orientation. When the array is turned on, the upper cell will have the opposite binary state from the lower cell. Thereafter, each cell can be respectively switched for storing ones and zeros in a normal RAM operating mode.Type: GrantFiled: December 29, 1982Date of Patent: November 29, 1983Assignee: IBM CorporationInventor: Jai P. Bansal