Patents by Inventor Jai Yong WOO

Jai Yong WOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory apparatus having open bit line structure in which a sense amplifier array shared between a dummy array and normal array,comparing one bit line of the normal array with two or more bit lines of the dummy array
    Patent number: 9666254
    Abstract: A semiconductor memory apparatus may include a memory bank having a plurality of memory cell arrays. The memory bank may have an open bit line structure. A sense amplifier array may be coupled in common with adjacent memory cell arrays. A sense amplifier coupled in common with a dummy array and a normal array may be coupled with one bit line disposed in the normal array and two bit lines disposed in the dummy array.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: May 30, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jai Yong Woo
  • SEMICONDUCTOR MEMORY APPARATUS HAVING OPEN BIT LINE STRUCTURE
    Publication number: 20170133069
    Abstract: A semiconductor memory apparatus may include a memory bank having a plurality of memory cell arrays. The memory bank may have an open bit line structure. A sense amplifier array may be coupled in common with adjacent memory cell arrays. A sense amplifier coupled in common with a dummy array and a normal array may be coupled with one bit line disposed in the normal array and two bit lines disposed in the dummy array.
    Type: Application
    Filed: February 2, 2016
    Publication date: May 11, 2017
    Inventor: Jai Yong WOO
  • Semiconductor device including capacitor and contact plug
    Patent number: 8686541
    Abstract: The present invention provides technology directed to a semiconductor device and a method of manufacturing the same. According to the present invention, metal contact plugs are formed to come into contact with both sidewalls of a capacitor, including lower electrodes, dielectric layers, and an upper electrode. Accordingly, contact resistance can be reduced because the contact area of the upper electrode and the metal contact plugs forming the capacitor, can be increased. Furthermore, the number of chips per wafer can be increased because the area in which the metal contact plugs and the capacitor are formed can be reduced. In addition, the generation of noise can be reduced because the contact area of the capacitor and the metal contact plugs is increased and thus voltage at the upper electrode is stabilized.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jai Yong Woo
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20120012981
    Abstract: The present invention provides technology directed to a semiconductor device and a method of manufacturing the same. According to the present invention, metal contact plugs are formed to come into contact with both sidewalls of a capacitor, including lower electrodes, dielectric layers, and an upper electrode. Accordingly, contact resistance can be reduced because the contact area of the upper electrode and the metal contact plugs forming the capacitor, can be increased. Furthermore, the number of chips per wafer can be increased because the area in which the metal contact plugs and the capacitor are formed can be reduced. In addition, the generation of noise can be reduced because the contact area of the capacitor and the metal contact plugs is increased and thus voltage at the upper electrode is stabilized.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 19, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jai Yong WOO