Abstract: A method and a system for transparently overlaying a logical transport network over an existing physical transport network is disclosed. The system designates a virtual channel located in a first transaction layer of a network conforming to a first network protocol. The system assembles a transaction layer packet in a second logical transaction layer of a second network protocol that is also recognizable by the first transaction layer. The system transfers the transaction layer packet from the second transaction layer to the virtual channel. The system transmits the transaction layer packet over the first transaction layer using the designated virtual channel over the network.

Abstract: A system and method for efficiently routing data in a communication fabric. A computing system includes a fabric for routing data among one or more agents and a memory controller for system memory. The fabric includes multiple hierarchical clusters with a split topology where the data links are physically separated from the control links. A given cluster receives a write command and associated write data, and stores them in respective buffers. The given cluster marks the write command as a candidate to be issued to the memory controller when it is determined the write data will arrive ahead of the write command at the memory controller after being issued. The given cluster prevents the write command from becoming a candidate to be issued when it is determined the write data may not arrive ahead of the write command at the memory controller.

Abstract: Various implementations of a multi-chip system operable according to a predefined transport protocol are disclosed. In one embodiment, a system comprises a first IC comprising a memory controller communicatively coupled with first physical ports. The system further comprises a second IC comprising second physical ports communicatively coupled with a first set of the first physical ports via first physical links, and one or more memory devices that are communicatively coupled with the second physical ports and accessible by the memory controller via the first physical links. The first IC further comprises an identification map table describing a first level of port aggregation to be applied across the first set. The second IC comprises a first distribution function configured to provide ordering to data communicated using the second physical ports. The first distribution function is based on the first level of port aggregation.

Abstract: A system and method for efficiently bridging two communication protocols. In various embodiments, a computing system includes an interconnect for routing traffic among agents and endpoints. The agents use a first communication protocol and the endpoints use a second communication protocol that differs from the first protocol with regard to at least the ordering that is enforced between transactions. A bridge selects transactions of a first type and a second type used in the first protocol for processing based on the first protocol ordering while using acknowledgments used by the second protocol.

Abstract: A system method of initializing operation of a semiconductor device including detecting de-assertion of an external reset signal while the semiconductor device in a reset state, monitoring a temperature level of the semiconductor device, and while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level, keeping the semiconductor device in the reset state and asserting at least one operating parameter on the semiconductor device at an elevated level to generate heat on the semiconductor device, and releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level. The operating parameter may be clock frequency or supply voltage level or a combination of both. Different elevated clock frequencies and/or different minimum operating temperature levels are contemplated.

Abstract: A system method of initializing operation of a semiconductor device including detecting de-assertion of an external reset signal while the semiconductor device in a reset state, monitoring a temperature level of the semiconductor device, and while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level, keeping the semiconductor device in the reset state and asserting at least one operating parameter on the semiconductor device at an elevated level to generate heat on the semiconductor device, and releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level. The operating parameter may be clock frequency or supply voltage level or a combination of both. Different elevated clock frequencies and/or different minimum operating temperature levels are contemplated.

Abstract: Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. In some embodiments of the present invention, operation translations coded relative to a particular logical I/O device, domain or sub-window seek to optimize functionality, isolation or some other figure of merit without regard to needs or limitations of another. In this way, operation translations need not be uniform and need not reduce supported operation semantics to correspond to that of a lowest common denominator I/O device. In some embodiments, the form of mappings (e.g.

Abstract: The disclosed embodiments relate to a secure configuration space for a computing device. Each of the configuration resisters in a configuration space are divided into security bits and configuration data bits. The security bits are assigned a predetermined value. When reading from or writing to a given configuration register, the data in the bit positions corresponding to security bits must match the predetermined values or read/write access is denied.

Abstract: A system includes a plurality of sources to provide information access requests. An arbiter includes an assignment module to associate a first access request from the first source to one of the plurality of arbitration slots based upon assignment information at a storage location, and a dispatch module to determine one request of a plurality of requests received at the plurality of sources to be dispatched to a resource, memory controller by a dispatch module.

Abstract: Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that are storage-efficient and which can provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. Indeed, different identifier and/or operation translation models may be employed on a per logical device (or even a per sub-window) basis. In general, the flexibility and efficiency afforded using some embodiments of the present invention can be desirable, particularly as numbers of I/O domains increase, such as in the case of virtualization system implementations in which a multiplicity of logical I/O devices may be represented using underlying physical resources.

Abstract: Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. In some embodiments of the present invention, operation translations coded relative to a particular logical I/O device, domain or sub-window seek to optimize functionality, isolation or some other figure of merit without regard to needs or limitations of another. In this way, operation translations need not be uniform and need not reduce supported operation semantics to correspond to that of a lowest common denominator I/O device. In some embodiments, the form of mappings (e.g.

Abstract: A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

Abstract: A method and architecture optimizes transaction ordering in a hierarchical bridge environment. A parent-bridge is one level above a child-bridge, which in turn is one level above a grand-child component. The parent-bridge is a bridge-bridge. The child-bridge can be a bus-bridge or a bridge-bridge. The grand-child component can be a bus, a bus-bridge or a bridge-bridge. A parent-bridge is connected to a child-bridge via child-links, the child-bridge connected to grandchild-links, and the parent-bridge having multiple transaction order queues (TOQs) per child-link. Ideally, the parent-bridge has one TOQ for each grandchild-link where the parent-bridge applies separate transaction ordering for each of the grandchild-links. However, at a minimum, the system uses at least two TOQs per child-link, and as such, provides a higher level of transaction throughput than systems using one TOQ per child-link. The child-bridge sends a signal to the parent-bridge identifying from which grandchild-link a transaction was sent.

Abstract: A technique is disclosed for facilitating data processing in a computer system. The technique utilizes logic to implement a dual mode design for PCI/PCI-X computer systems that enables optimal efficiency in regardless of which mode the system is operating in. The technique involves the implementation of two sets of transmitting and receiving elements, one tuned to PCI protocol timing and the other to PCI-X protocol. Therefore, allowing the system to process both PCI and PCI-X transactions without adversely affecting the other functional mode. The technique also enables an operator to adjust the clock timing separately for each protocol without having a detrimental affect on the other operating protocol.

Abstract: The disclosed embodiments relate to a secure configuration space for a computing device. Each of the configuration resisters in a configuration space are divided into security bits and configuration data bits. The security bits are assigned a predetermined value. When reading from or writing to a given configuration register, the data in the bit positions corresponding to security bits must match the predetermined values or read/write access is denied.

Abstract: A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

Abstract: A method and architecture optimizes transaction ordering in a hierarchical bridge environment. A parent-bridge is one level above a child-bridge, which in turn is one level above a grand-child component. The parent-bridge is a bridge-bridge. The child-bridge can be a bus-bridge or a bridge-bridge. The grand-child component can be a bus, a bus-bridge or a bridge-bridge. A parent-bridge is connected to a child-bridge via child-links, the child-bridge connected to grandchild-links, and the parent-bridge having multiple transaction order queues (TOQs) per child-link. Ideally, the parent-bridge has one TOQ for each grandchild-link where the parent-bridge applies separate transaction ordering for each of the grandchild-links. However, at a minimum, the system uses at least two TOQs per child-link, and as such, provides a higher level of transaction throughput than systems using one TOQ per child-link. The child-bridge sends a signal to the parent-bridge identifying from which grandchild-link a transaction was sent.

Abstract: A technique is disclosed for facilitating data processing in a computer system. The technique utilizes logic to implement a dual mode design for PCI/PCI-X computer systems that enables optimal efficiency in regardless of which mode the system is operating in. The technique involves the implementation of two sets of transmitting and receiving elements, one tuned to PCI protocol timing and the other to PCI-X protocol. Therefore, allowing the system to process both PCI and PCI-X transactions without adversely affecting the other functional mode. The technique also enables an operator to adjust the clock timing separately for each protocol without having a detrimental affect on the other operating protocol.