Patents by Inventor Jaideep DUTT

Jaideep DUTT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Identifying RTL code that can be a source of verification complexity for downstream equivalence checkers and generating recommendations to improve runtime of equivalence checkers
    Patent number: 12682143
    Abstract: Aspects of the present disclosure relate to improving runtime performance of equivalence checkers by a shift left process that uses an RTL lint tool to identify RTL code that can be a source of verification complexity for the downstream equivalence checker. The RTL code is further compared to a corresponding circuit model to determine a potential gate-level location of the potentially problematic RTL code. A weight can be calculated to represent a level of verification complexity that may be generated by the particular portion of the RTL code. Further, one or more recommendations can be generated by the RTL lint tool to prevent some of the verification complexity for the downstream equivalence checker.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: July 14, 2026
    Assignee: Synopsys, Inc.
    Inventors: Himanshu Kathuria, Makarand Patil, Rohit Kumar Ohlayan, Paras Mal Jain, Ila Verma, Mohan Mangal, Jaideep Dutt, Jaskaran Singh Ajimal, Harpreet Singh Anand
  • IDENTIFYING RTL CODE THAT CAN BE A SOURCE OF VERIFICATION COMPLEXITY FOR DOWNSTREAM EQUIVALENCE CHECKERS AND GENERATING RECOMMENDATIONS TO IMPROVE RUNTIME OF EQUIVALENCE CHECKERS
    Publication number: 20240320406
    Abstract: Aspects of the present disclosure relate to improving runtime performance of equivalence checkers by a shift left process that uses an RTL lint tool to identify RTL code that can be a source of verification complexity for the downstream equivalence checker. The RTL code is further compared to a corresponding circuit model to determine a potential gate-level location of the potentially problematic RTL code. A weight can be calculated to represent a level of verification complexity that may be generated by the particular portion of the RTL code. Further, one or more recommendations can be generated by the RTL lint tool to prevent some of the verification complexity for the downstream equivalence checker.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Inventors: Himanshu KATHURIA, Makarand PATIL, Rohit Kumar OHLAYAN, Paras Mal JAIN, Ila VERMA, Mohan MANGAL, Jaideep DUTT, Jaskaran Singh AJIMAL, Harpreet Singh ANAND