Abstract: High frequency laser diode (LD) and electro-absorption modulator (EAM) integrated circuit drivers using a cascaded output switch architecture that increases the output current and voltage edge speed and reduces the peaking and ringing of the output waveform, thus improving the deterministic jitter performance. Also disclosed is a method and apparatus that provides a modulation current dependence of both turn-on and turn-off driving currents that lead to an optimal compromise between the edge speed and output overshoot for a wide range of modulation currents. A PTAT temperature dependence of both voltage swing and current level in the predriver assures a low variation of the overshoot and rise/fall time over a wide temperature range. Using the cascaded output switch architecture provides an easy way of on-chip summation of the modulation and bias currents. Biasing the cascode device with a supply and modulation current dependent base voltage provides an optimum headroom output switch.

Abstract: A circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.

Abstract: A precise current cell for a digital-to-analog (D/A) convertor circuit is designed to compensate for manufacturing process variations. The cell uses a cascoded transistor chain to control the output voltage and isolate voltage supply noise. An external (off-chip) bias current is fed into a cascoded biasing string of eight transistors, which are further mirrored to the current cell itself. The biasing scheme accounts for manufacturing process variations in the chip, which leads to very precise current being replicated at the output of the D/A circuit. Current steering and an improved shunt path within the current cell minimizes voltage swings during switching of the current cell. This allows for faster switching of the cell while minimizing noise coupling due to the voltage swings. The current cell also has an associated biasing stage. This biasing stage allows for improved matching within the current cell, resulting in improved accuracy of conversion.

Abstract: A monolithic device is shown having a number of phase locked loops (PLLs) constructed thereon. At least one of the PLLs is constructed as a multiple loop having an output of one PLL loop tied back to the feedback path of the other loop of the pair. In this manner, tight resolution can be obtained in one loop while the bandwidth of that loop is coarse. The bandwidth of the second loop is tight, thereby giving good resolution to the first loop while still avoiding the problems inherent with noise injection locking from other PLLs on the same device.

Abstract: A system and method for establishing the frequency of a voltage controlled oscillator ("VCO") within narrowly defined frequency bands. The resonant circuit of the VCO uses selectable elements, such as varactor diodes, to establish the operating frequency band. The control voltage of the VCO is varied within a voltage range to adjust the VCO output frequency. A phase detector compares the VCO output to a reference signal. If the phase detector determines that there is an imbalance between the VCO output and the reference signal, then it produces a signal which indicates whether the VCO frequency should be increased or decreased to match the reference signal frequency. If the control voltage is outside of the voltage range, then the system allows the operating frequency band to be changed by varying the number of selectable elements in response to the phase detector signal.

Abstract: The system and method for phase lock loop (PLL) gain stabilization uses a digital compensation technique to correct for the large amount of gain variation present in a voltage controlled oscillator (VCO) utilizing a varactor diode. AVCO is arranged with additional capacitance in parallel with the vatactor diode of the VCO. By using multiple capacitors, more or less capacitance can be switched into parallel with the vatactor diode. Gain variation is accomplished by switching capacitors into the circuit, and for each combination of capacitors used in the resonant inductance-capacitance (LC) circuit of the VCO, the gain of the phase detector in the PLL is adjusted simultaneously. The phase detector has a charge pump that drives a current into a loop filter having a capacitor with a fixed value. The gain adjustment is accomplished by varying the amount of current available from the charge pump to this filter capacitor.

Abstract: A single-port network node transceiver that does not draw any substantial current from the network when it is powered-down, enabling it to meet the ISDN powered-down loading specification when built on a CMOS integrated circuit chip. The pull-up transistors of the transmitter output circuit each have means for shorting the well terminal to source terminal connection when the circuit is operating and opening the connection when the power to the transceiver is shut down. The opening of this connection prevents the well-substrate junction of the pull-up transistors from becoming forward biased and drawing current from the network when the power to the transceiver is off and there is voltage present on the network. The transceiver also includes a plurality of ESD overvoltage protection diodes in series between the power supply rail and each input/output terminal.