Abstract: The present disclosure relates to a test response compaction scheme and, more particularly, to a test response compaction scheme for integrated circuits with improved diagnostic capability and test time, with related structures and processes. The method includes: arranging bits of a memory cell into channels and clock cycles, wherein each clock cycle is assigned a successive prime number and each channel has a maximum chain length of “X” number of bits; performing a test by applying stimulus and capturing response in memory elements; scanning out test results of the test performed on the bits for each cycle and channel; calculating a final signature of the test results using the successive prime number and a weighting afforded to each channel; and identifying any failures of the bits by comparing the final signature to an expected signature.