Patents by Inventor Jaiganesh Balakrishnan

Jaiganesh Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10555256
    Abstract: A re-sampler comprises a first CSD multiplier configured to receive input samples, a first accumulator coupled to the first CSD multiplier and configured to form a first MAC unit with the first CSD multiplier, a second CSD multiplier configured to receive the input samples, and a second accumulator coupled to the second CSD multiplier and configured to form a second MAC unit with the second CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. A method comprises receiving, by a first CSD multiplier, input samples, receiving, by a second CSD multiplier, the input samples, generating coefficients, scaling, using the first CSD multiplier and the second CSD multiplier, the input samples with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples, and generating output samples based on the coefficient vector scaled input samples. The CSD multipliers may be MC-CSD multipliers.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: February 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Jawaharlal Tangudu, Sreenath Potty Narayanan
  • Patent number: 10541703
    Abstract: An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange).
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sthanunathan Ramakrishnan, Sashidharan Venkatraman, Jaiganesh Balakrishnan, Sreenath Narayanan Potty
  • Publication number: 20200007365
    Abstract: IQ mismatch correction for analog chain IQ mismatch impairments is based on a two-filter architecture. In either RX or TX, an IQmc mismatch corrector (digital chain) filters I and Q digital signals, and includes an I-path to receive the I signal, and a Q-path to receive the Q signal, and is configured with two filters: an in-path filter to filter either the I signal or the Q signal received in the same path; and a cross-path filter to filter either the I signal or the Q signal received in the other path. The IQmc mismatch corrector can include: an I-path delay element to provide a delay to the I signal corresponding to a delay through either the in-path filter or the cross-path filter; and a Q-path delay element to provide a delay to the Q signal corresponding to a delay through either the in-path filter or the cross-path filter.
    Type: Application
    Filed: April 4, 2019
    Publication date: January 2, 2020
    Inventors: Jawaharlal Tangudu, Sthanunathan Ramakrishnan, Jaiganesh Balakrishnan
  • Patent number: 10505582
    Abstract: Signal compression for serialized data bandwidth reduction based on decomposition of a data signal into separate signal components with different SQNR or dynamic range requirements, and quantizing the signal components with different bit precisions. Compression logic decomposes the input data signal into the first/second signal components, quantizes the first component with a pre-defined first bit precision to provide a first quantized data signal, quantizes the second component with a pre-defined second bit precision to provide a second quantized data signal, the second bit precision less than the first bit precision, the first and second quantized data signals bit packed into a compressed digital data signal.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 10, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sarma Sundareswara Gunturi, Jaiganesh Balakrishnan
  • Patent number: 10483997
    Abstract: A method for frequency domain to time domain conversion includes receiving a set of frequency-domain samples. Based on the set of frequency-domain samples, a first sample subset comprising a predetermined fraction of the number of samples of the set of frequency-domain samples and a second sample subset comprising the predetermined fraction of the number of samples of the set of frequency-domain samples are generated. A linear phase rotation is applied to the first sample subset and the second sample subset to produce a phase rotated first sample subset and a phase rotated second sample subset. The phase rotated first sample set is post-processed to generate a first set of time-domain samples. The phase rotated second sample set is post-processed to generate a second set of time-domain samples. The first set of time-domain samples and the second set of time-domain samples are reordered to produce an output set of time-domain samples.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind Ganesan, Jaiganesh Balakrishnan, Sashidharan Venkatraman, Bragadeesh Suresh Babu
  • Patent number: 10484224
    Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Sarma Sundareswara Gunturi, Pankaj Gupta, Indu Prathapan
  • Publication number: 20190317731
    Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Jawaharlal Tangudu, Suvam Nandi, Pooja Sundar, Jaiganesh Balakrishnan
  • Publication number: 20190280675
    Abstract: A zero-insertion FIR filter architecture for filtering a signal with a target band and a secondary band. Digital filter circuitry includes an L-tap FIR (finite impulse response) filter, with a number L filter tap elements (L=0, 1, 2, . . . (L?1)), each with an assigned coefficient from a defined coefficient sequence. The L-tap FIR filter is configurable with a defined zero-insertion coefficient sequence of a repeating sub-sequence of a nonzero coefficient followed by one or more zero-inserted coefficients, with a number Nj of nonzero coefficients, and a number Nk of zero-inserted coefficients, so that L=Nj+Nk. The L-tap FIR filter is configurable as an M-tap FIR filter with a nonzero coefficient sequence in which each of the L filter tap elements is assigned a non-zero coefficient, the M-tap FIR filter having an effective length of M=(Nj+Nk) non-zero coefficients.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 12, 2019
    Inventors: Jawaharlal Tangudu, Jaiganesh Balakrishnan
  • Publication number: 20190273601
    Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventors: Jaiganesh BALAKRISHNAN, Shagun DUSAD, Visvesvaraya PENTAKOTA, Srinivas Kumar Reddy NARU, Sarma Sundareswara GUNTURI, Nagalinga Swamy Basayya AREMALLAPUR
  • Patent number: 10396829
    Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 27, 2019
    Assignee: TEXAS INTSTUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
  • Patent number: 10371528
    Abstract: Devices and methods for pedestrian navigation are disclosed. In an embodiment, a device includes an accelerometer sensor configured to sense acceleration components associated with a device motion in a plurality of axes of the accelerometer sensor. The acceleration components include stride frequency components and step frequency components. The device includes a processing module communicably associated with the accelerometer sensor. The processing module is configured to process at least a portion of the acceleration components to determine an estimated attitude associated with the device motion with respect to the accelerometer sensor. The processing module is configured to filter out the step frequency components by blocking the stride frequency components. The processing module is further configured to determine the estimated attitude based on the step frequency components to thereby mitigate a bias in the estimated attitude associated with a lateral sway of the device motion.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jayawardan Janardhanan, Jaiganesh Balakrishnan
  • Patent number: 10372415
    Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jawaharlal Tangudu, Suvam Nandi, Pooja Sundar, Jaiganesh Balakrishnan
  • Publication number: 20190214972
    Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.
    Type: Application
    Filed: March 12, 2019
    Publication date: July 11, 2019
    Inventors: Jaiganesh Balakrishnan, Sthanunathan Ramakrishnan, Pooja Sundar, Sashidharan Venkatraman
  • Patent number: 10341082
    Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Shagun Dusad, Visvesvaraya Pentakota, Srinivas Kumar Reddy Naru, Sarma Sundareswara Gunturi, Nagalinga Swamy Basayya Aremallapur
  • Patent number: 10341953
    Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Sarma Sundareswara Gunturi
  • Publication number: 20190181842
    Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Inventors: Sundarrajan RANGACHARI, Jaiganesh BALAKRISHNAN, Jawaharlal TANGUDU, Srinivas Kumar Reddy NARU
  • Publication number: 20190178993
    Abstract: A three dimensional time of flight (TOF) camera includes a transmitter and a receiver. The transmitter is configured to generate an electrical transmit signal at a plurality of frequencies over an integration time period and generate a transmit optical waveform corresponding with the electrical transmit signal. The receiver is configured to receive a reflected optical waveform that is the transmit optical waveform reflected off of an object, integrate the reflected optical waveform over the integration time period, and determine a distance to the target object based on a TOF of the optical waveform. The integration time period includes exposure time periods. A length of each of the exposure time periods corresponds to one of the frequencies. The TOF is determined based on a correlation of the electrical transmit signal and the return optical waveform utilizing a correlation function with respect to the integration time period.
    Type: Application
    Filed: December 7, 2017
    Publication date: June 13, 2019
    Inventors: Subhash Chandra Venkata SADHU, Bharath PATIL, Jaiganesh BALAKRISHNAN
  • Publication number: 20190175037
    Abstract: An apparatus to detect a heart rate of a user includes a motion detection circuit configured to generate a motion status signal indicative of a motion status of the user. The apparatus also comprises a filter circuit coupled to the motion detection circuit that is configured to generate a filter circuit output signal based on dynamically variable. The coefficients are dependent on the motion status signal and a first signal received by the filter circuit. The apparatus also comprises a combination circuit coupled to the filter circuit and configured to receive a second signal indicative of the ambient light, the motion of the user, and non-ambient light reflected from the user. The combination circuit is configured to determine a difference between the second signal and the filter circuit output signal to generate a combination circuit output signal.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 13, 2019
    Inventors: Sarma Sundareswara GUNTURI, Jaiganesh BALAKRISHNAN
  • Patent number: 10305451
    Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 28, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sundarrajan Rangachari, Jaiganesh Balakrishnan, Jawaharlal Tangudu, Srinivas Kumar Reddy Naru
  • Patent number: 10277202
    Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: April 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Sthanunathan Ramakrishnan, Pooja Sundar, Sashidharan Venkatraman