Patents by Inventor Jai-Hyuk Song
Jai-Hyuk Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11728220Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.Type: GrantFiled: October 26, 2021Date of Patent: August 15, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Gn Yun, Jae-Duk Lee, Jai-Hyuk Song
-
Publication number: 20220045101Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.Type: ApplicationFiled: October 26, 2021Publication date: February 10, 2022Inventors: JANG-GN YUN, JAE-DUK LEE, JAI-HYUK SONG
-
Patent number: 11189632Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.Type: GrantFiled: November 6, 2019Date of Patent: November 30, 2021Inventors: Jang-Gn Yun, Jae-Duk Lee, Jai-Hyuk Song
-
Publication number: 20200273501Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.Type: ApplicationFiled: November 6, 2019Publication date: August 27, 2020Inventors: Jang-gn YUN, Jae-Duk LEE, Jai-Hyuk SONG
-
Patent number: 9824759Abstract: In a method of programming a non-volatile memory device, a first voltage is applied to a selected memory cell for programming, and a second voltage is applied to a non-selected memory cell. Before the second voltage rises to a predetermined voltage level, which is less than a program voltage level, the first voltage is greater than the second voltage or the second voltage is maintained at greater than a ground voltage level. Related non-volatile memory devices and memory systems are also discussed.Type: GrantFiled: January 29, 2015Date of Patent: November 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-woong Kwon, Jai-hyuk Song, Chang-sub Lee
-
Patent number: 8488386Abstract: Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select line; a first word line adjacent to the dummy word line; and a second word line disposed between the string select line and the first word line. The nonvolatile memory device is configured to apply a voltage to the dummy word line. When programming a memory cell connected to the first word line, a first dummy word line voltage lower than a voltage applied to the second word line is applied to the dummy word line. When programming a memory cell connected to the second word line, a second dummy word line voltage between a voltage applied to the first word line and the first dummy word line voltage is applied to the dummy word line.Type: GrantFiled: March 10, 2011Date of Patent: July 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hoon Kim, Jai-Hyuk Song, Yong-Joon Choi
-
Patent number: 8456918Abstract: An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL<i>, a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL<i> increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors.Type: GrantFiled: March 17, 2009Date of Patent: June 4, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Yean Oh, Woon-Kyung Lee, Jai Hyuk Song, Chang-Sub Lee
-
Publication number: 20120318567Abstract: A wiring structure includes a first plug extending through a first insulating interlayer on a substrate, a first wiring extending through a second insulating interlayer on the first insulating interlayer and the first wiring is electrically connected to the first plug, a diffusion barrier layer pattern on the first wiring and on the second insulating interlayer, a portion of the second insulating interlayer being free of being covered by the diffusion barrier layer pattern, a second plug extending through the diffusion barrier layer pattern, the second plug is in contact with the first wiring, and a second wiring electrically connected to the second plug.Type: ApplicationFiled: June 13, 2012Publication date: December 20, 2012Inventors: Jong-Hyun PARK, Jee-Yong KIM, Joon-Hee LEE, Jai-Hyuk SONG, Sang-Youn JO
-
Patent number: 8324052Abstract: A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.Type: GrantFiled: January 20, 2011Date of Patent: December 4, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Yean Oh, Jai-Hyuk Song, Chang-Sub Lee, Chang-Hyun Lee, Hyun-Jae Kim
-
Publication number: 20120142177Abstract: A method of manufacturing a wiring structure and a semiconductor device, the method of manufacturing a wiring structure including forming a first insulating interlayer on a substrate; forming a contact plug in an opening in the first insulating interlayer; forming a second insulating interlayer on the contact plug and the first insulating interlayer; removing a portion of the second insulating interlayer to form an opening therethrough such that the opening exposes the contact plug; filling a portion of the opening to form a wiring such that the wiring is electrically connected to the contact plug; and forming a diffusion barrier layer pattern on the wiring such that the diffusion barrier layer pattern fills a remaining portion of the opening.Type: ApplicationFiled: November 18, 2011Publication date: June 7, 2012Inventors: Jee-Yong Kim, Joon-Hee Lee, Jeong-Hyuk Choi, Jai-Hyuk Song, Seung-Wan Hong, Hwa-Eon Shin, Jong-Hyun Park, Woo-Jung Kim, Jae-Sung Ahn, Jung-Hwan Lee
-
Publication number: 20110222339Abstract: Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select line; a first word line adjacent to the dummy word line; and a second word line disposed between the string select line and the first word line. The nonvolatile memory device is configured to apply a voltage to the dummy word line. When programming a memory cell connected to the first word line, a first dummy word line voltage lower than a voltage applied to the second word line is applied to the dummy word line. When programming a memory cell connected to the second word line, a second dummy word line voltage between a voltage applied to the first word line and the first dummy word line voltage is applied to the dummy word line.Type: ApplicationFiled: March 10, 2011Publication date: September 15, 2011Inventors: Sung-Hoon Kim, Jai-Hyuk Song, Yong-Joon Choi
-
Publication number: 20110111570Abstract: A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.Type: ApplicationFiled: January 20, 2011Publication date: May 12, 2011Inventors: Dong-Yean Oh, Jai-Hyuk Song, Chang-Sub Lee, Chang-Hyun Lee, Hyun-Jae Kim
-
Patent number: 7898039Abstract: A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.Type: GrantFiled: February 15, 2007Date of Patent: March 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Yean Oh, Jai-Hyuk Song, Chang-Sub Lee, Chang-Hyun Lee, Hyun-Jae Kim
-
Patent number: 7867849Abstract: Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.Type: GrantFiled: August 1, 2008Date of Patent: January 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Ho Lee, Jai-Hyuk Song, Dong-Uk Choi, Suk-Kang Sung
-
Patent number: 7687860Abstract: There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode of the select transistor opposite to the memory transistor has nearly a box-shaped figure. In order to form the floating gate of the memory transistor in shape of the inverted T, a region for the select transistor is closed when opening a region for the memory transistor.Type: GrantFiled: June 21, 2006Date of Patent: March 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Woon-Kyung Lee, Jeong-Hyuk Choi, Dong-Jun Lee, Jai-Hyuk Song
-
Patent number: 7683422Abstract: Non-volatile memory devices include memory cells therein with reduced cell-to-cell coupling capacitance. These memory cells include floating gate electrodes with open-ended wraparound shapes that operate to reduce the cell-to-cell coupling capacitance in a bit line direction, while still maintaining a high coupling ratio between control and floating gate electrodes within each memory cell.Type: GrantFiled: August 14, 2006Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Woon-Kyung Lee, Jeong-Hyuk Choi, Jai-Hyuk Song
-
Patent number: 7678650Abstract: Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.Type: GrantFiled: May 20, 2009Date of Patent: March 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-Won Koh, Byung-Hong Chung, Sang-Gyun Woo, Jeong-Lim Nam, Seok-Hwan Oh, Jai-Hyuk Song, Hyun Park, Yool Kang
-
Publication number: 20090257280Abstract: An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL<i>, a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL<i> increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors.Type: ApplicationFiled: March 17, 2009Publication date: October 15, 2009Inventors: Dong-Yean Oh, Woo-Kyung Lee, Jai Hyuk Song, Chang-Sub Lee
-
Publication number: 20090258473Abstract: Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.Type: ApplicationFiled: May 20, 2009Publication date: October 15, 2009Inventors: Cha-Won Koh, Byung-Hong Chung, Sang-Gyun Woo, Jeong-Lim Nam, Seok-Hwan Oh, Jai-Hyuk Song, Hyun Park, Yool Kang
-
Patent number: 7589374Abstract: Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.Type: GrantFiled: January 31, 2007Date of Patent: September 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jai-Hyuk Song, Jeong-Hyuk Choi, Woon-Kyung Lee