Abstract: A method of precleaning a silicon wafer to remove a layer of native silicon oxide thereon comprising adding a mixture of argon and oxygen to a plasma etch chamber including a wafer to be cleaned mounted on a cathode in said chamber, while maintaining the pressure in the chamber below about 3 millitorr. The oxygen is added to react with silicon atoms in the plasma but not with silicon atoms of the single crystal silicon wafer. The presence of oxygen in the plasma at low pressure ensures steady plasma generation and uniform etching across the wafer.

Abstract: A deposition rate monitor based on the measurement of optical attenuation is described for use in deposition equipment such as sputtering systems used to deposit thin metal films on semiconductor devices. A beam of light is passed through the region between a deposition source and the deposition substrate. The beam of light is attenuated by the material being transported from the source to the substrate before the light is detected at a detector. The level of attenuation of the light passing through the deposition environment can be empirically related to the rate at which material is being deposited on the substrate. The optical absorption deposition rate monitor can be used to adjust processing variables to maintain a constant deposition rate.

Abstract: A method for metallizing semiconductor materials includes two processing steps. In the first step, a layer of an alloy of conductive metal, such as aluminum, and an Alloy Material such as hafnium, tantalum, magnesium, germanium, silicon, titanium, titanium nitride, tungsten and/or a composite of tungsten, is deposited on the surface in a single step from a single source. In the second step, a layer of the conductive metal is deposited over the alloy layer. Thus, using this method, metallization can be conveniently performed using two chambers.

Abstract: Apparatus and methods for measuring the sheet resistance of an electrically conductive film on a semiconductor substrate while maintaining the substrate within the vacuum environment of the semiconductor process apparatus. In one aspect of the invention, the conductive film is deposited on the substrate within a vacuum chamber, and the resistance probe is located within the same chamber. The probe retracts out of the way during deposition of the film, and then moves to the substrate to measure the resistance of the film after deposition is paused or completed. In a second aspect of the invention, the probe is located in a chamber other than the chamber which deposits the conductive film.

Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.

Abstract: A method of precleaning a wafer including the steps of placing the wafer in a plasma chamber; flowing a gas into the plasma chamber; establishing a plasma in the chamber at a first pressure; after establishing the plasma, plasma etching the wafer at the first pressure for a first period of time; transitioning to a second pressure that is different from the first pressure; plasma etching the wafer at the second pressure for a second period of time; and after the second period of time has elapsed, discontinuing plasma etching at the second pressure.

Abstract: An improved clamping ring, useful for securing a semiconductor wafer during wafer processing, for example in a physical vapor deposition system, is made of a thermally nonconductive material having a low thermal coefficient of expansion, for example a ceramic material, such as alumina. Such material, by exhibiting only slight expansion or contraction during thermal cycling, allows the production of a clamping ring having the largest possible inner diameter, such that more wafer surface area is available for device fabrication, and such that wafer shadowing that results from metal film build-up on the clamping ring is mitigated, thereby extending the useful life of the clamp ring and reducing system downtime. Additionally, the thermal stability provided by the present invention improves wafer temperature uniformity, and therefore also improves per wafer device yield while increasing device reliability.

Abstract: A method for metallizing semiconductor materials includes two processing steps. In the first step, a layer of an alloy of conductive metal, such as aluminum, and refractory metal, such as titanium, tungsten or silicon, is deposited on the surface in a single step from a single source. In the second step, a layer of the conductive metal is deposited over the alloy layer. Thus, using this method, metallization can be conveniently performed using two chambers.

Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.

Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.

Abstract: An improved process is described for forming planar tungsten-filled contacts to a silicon substrate in contact openings through an insulating layer which provides for the formation of titanium silicide in and on the silicon surface at the bottom of the contact openings to provide low resistance silicide interconnections between the silicon substrate and the tungsten. A titanium nitride layer is formed over the titanium silicide and on the surfaces of the insulation layer, including the top surface of the insulation layer and the sidewall surfaces of the contact openings through the insulating layer. This titanium nitride layer provides a nucleation layer which permits a good bond to form from the tungsten through the titanium nitride and titanium silicide in the contact openings to the silicon substrate; and from the tungsten through the titanium nitride layer to the insulator material such as silicon dioxide (SO.sub.2), resulting in the formation of low resistance and low defect density contacts.

Abstract: A process is described for forming an aluminum plug in a via in an insulating layer in an integrated circuit structure by first depositing a layer of aluminum over the insulating layer in a multistep deposition which will also result in filling the via with aluminum to form an aluminum plug therein, followed by removal of any additional aluminum formed over the surface of the insulating layer, and subsequent formation of one or more patterned conductive layers over the insulating surface which is in electrical communication with the underlying aluminum plug in the via. The one or more patterned conductive layers formed over the insulating surface are characterized by superior electrical properties over the aluminum layer initially deposited and then removed. A barrier layer may be first formed over exposed portions of the underlying integrated circuit structure at the bottom of the via before it is filled with aluminum.

Abstract: An improved process is described for forming planar tungsten-filled contacts to a silicon substrate in contact openings through an insulating layer which provides for the formation of titanium silicide in and on the silicon surface at the bottom of the contact openings to provide low resistance silicide interconnections between the silicon substrate and the tungsten. A titanium nitride layer is formed over the titanium silicide and on the surfaces of the insulation layer, including the top surface of the insulation layer and the sidewall surfaces of the contact openings through the insulating layer. This titanium nitride layer provides a nucleation layer which permits a good bond to form from the tungsten through the titanium nitride and titanium silicide in the contact openings to the silicon substrate; and from the tungsten through the titanium nitride layer to the insulator material such as silicon dioxide (SO.sub.2), resulting in the formation of low resistance and low defect density contacts.

Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.

Abstract: A process is disclosed for forming a layer of titanium nitride on a semiconductor wafer which comprises forming a titanium layer on the wafer in a vacuum deposition chamber in the substantial absence of oxygen-bearing gases; transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; annealing the titanium-coated semiconductor wafer in a nitrogen-bearing atmosphere in the sealed annealing chamber, and in the substantial absence of oxygen-bearing gases, at an annealing temperature of from 400.degree. C. up to below about 650.degree. C. to form a titanium nitride compound on the wafer; and further annealing the wafer at a temperature of from about 800.degree. C. to about 900.degree. C. to form a stable phase of stoichiometric titanium nitride (TiN) on the wafer.

Abstract: The temperature of a semiconductor wafer during annealing of metallization is accurately and indirectly monitored by supporting the wafer on a thin susceptor of constant emissivity and monitoring the temperature of the susceptor. The system has the added advantage of providing efficient, controlled heating of the wafer by radiant heating of the backside of the susceptor.

Abstract: An improved process is disclosed for forming a conductive layer of titanium silicide on a silicon semiconductor wafer using a single annealing step which comprises the steps of forming a titanium layer over the wafer in a vacuum deposition chamber in the substantial absence of oxygen-bearing gases; transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; and then annealing the titanium-coated silicon semiconductor wafer in a nitrogen-bearing atmosphere in the sealed annealing chamber at a first temperature of from about 500.degree. C. to about 695.degree. C., in the substantial absence of oxygen-bearing gases, to form a titanium silicide layer and a titanium nitride layer over the titanium silicide which inhibits migration of underlying silicon to the surface, and to react substantially all of the titanium overlying silicon oxide (SiO.sub.

Abstract: An improved method and apparatus are disclosed for calibrating the emissivity characteristics of a semiconductor wafer within a processing chamber by supporting a sample wafer on a graphite susceptor within the chamber and by comparing the temperature measured within the susceptor in close proximity to the center of the wafer with the temperature measured by the emission of radiation from the surface of the wafer through the walls of the processing chamber. Temperature measurements subsequently made from the radiation emitted from the surface of similar wafers are corrected with reference to the measurement made of the temperature within the susceptor on the sample wafer.

Abstract: Radiation detectors and method measure the emissivity of a remote, heated semiconductor wafer in the presence of ambient radiation. Incident radiation within a selected waveband from a controlled source intermittently radiates the remote wafer, and reflected radiation therefrom is detected in synchronism with the intermittent incident radiation to yield output indications of emissivity of the wafer under varying processing conditions. The temperature of the wafer is monitored by another radiation detector (or detectors) operating substantially within the same selected waveband, and the temperature indications thus derived are corrected in response to the output indications of emissivity to provide indications of the true temperature of the wafer.

Abstract: An improved method and apparatus are disclosed for calibrating the emissivity characteristics of a semiconductor wafer within a processing chamber by supporting a sample wafer on a graphite susceptor within the chamber and by comparing the temperature measured within the susceptor in close proximity to the center of the wafer with the temperature measured by the emission of radiation from the surface of the wafer through the walls of the processing chamber. Temperature measurements subsequently made from the radiation emitted from the surface of similar wafers are corrected with reference to the measurement made of the temperature within the susceptor on the sample wafer.