Patents by Inventor Jaime Bayan
Jaime Bayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090160037Abstract: A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Jaime A. BAYAN, Anindya PODDAR
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Publication number: 20090160039Abstract: A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Will K. WONG, Nghia T. TU, Jaime A. BAYAN
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Publication number: 20090115035Abstract: Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.Type: ApplicationFiled: November 6, 2007Publication date: May 7, 2009Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Jaime A. BAYAN, Anindya Poddar
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Patent number: 7491625Abstract: A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the first tape to provide a multiplicity of individual dice. The active surfaces of the singulated dice are then adhered to a second tape with the first tape still adhered to the back surfaces of the dice. The first tape may then be removed. In this manner, the back surfaces of the dice may be left exposed and facing upwards with the active surfaces of the dice adhered to the second tape. The described method permits the use of a conventional die attach machine that is not designated for use as a flip-chip die attach machine.Type: GrantFiled: March 26, 2007Date of Patent: February 17, 2009Assignee: National Semiconductor CorporationInventors: Jaime A. Bayan, Nghia Tu, Anindya Poddar, Ashok Prabhu
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Publication number: 20080290482Abstract: A method of packaging integrated circuit dice into exposed die packages is described. The method includes depositing a metallic layer onto the back surface of an integrated circuit wafer such that it covers the back surface. The method additionally includes applying a protective layer over the metallic layer such that the protective layer covers the metallic layer. The method further includes singulating the wafer to produce individual dice. Each die may then be electrically connected to a lead frame. The die and portions of the lead frame may then be encapsulated with a molding compound. The protective layer inhibits the molding compound from contacting the metallic layer on the back surface of the die. The protective layer is then removed from the metallic layer. As a result, an individual IC package is produced that includes a die having a metallic layer exposed on the back surface of the die.Type: ApplicationFiled: September 19, 2007Publication date: November 27, 2008Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Jaime A. Bayan, Nghia Tu, Will K. Wong
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Patent number: 7432583Abstract: A semiconductor package is provided with an internal package formed in the cavity of the external leadless leadframe package (LLP). The internal package is a leadless leadframe package and provides a substrate for mounting one or more die and passive devices to form the external LLP. By arranging the die and passive components on the internal package, higher chip density and a smaller form factor may be achieved.Type: GrantFiled: July 8, 2004Date of Patent: October 7, 2008Assignee: National Semiconductor CorporationInventors: Felix C. Li, Jaime A. Bayan
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Publication number: 20080241993Abstract: A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the first tape to provide a multiplicity of individual dice. The active surfaces of the singulated dice are then adhered to a second tape with the first tape still adhered to the back surfaces of the dice. The first tape may then be removed. In this manner, the back surfaces of the dice may be left exposed and facing upwards with the active surfaces of the dice adhered to the second tape. The described method permits the use of a conventional die attach machine that is not designated for use as a flip-chip die attach machine.Type: ApplicationFiled: March 26, 2007Publication date: October 2, 2008Inventors: Jaime A. Bayan, Nghia Tu, Anindya Poddar, Ashok Prabhu
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Publication number: 20080237814Abstract: An integrated circuit package is described that includes a die and a lead frame that includes recessed regions for preventing the undesired spread of solder during reflow. The die includes a plurality of solder bumps formed on its active surface. The lead frame includes a plurality of leads, each having an associated solder pad. Each solder pad is suitably positioned adjacent and electrically contacting an associated solder bump on the die. Each lead also includes a recessed region in a region adjacent to the solder pad. The recessed region serves to isolate the surface of the solder pad from the other surfaces of the lead. In this manner, the solder of the solder bump that contacts the lead is confined to the surface of the associated solder pad.Type: ApplicationFiled: March 26, 2007Publication date: October 2, 2008Inventor: Jaime A. Bayan
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Publication number: 20080241991Abstract: An improved method and apparatus for packaging integrated circuits are described. More particularly, a method and apparatus for use in securing a plurality of integrated circuit dice to a lead frame panel are described. Each integrated circuit die includes an active surface having a multiplicity of solder bumps. The lead frame panel includes an array of device areas, each including a plurality of leads. The method includes positioning a plurality of dice into designated positions on a carrier such that the active surfaces of the dice are facing upwards. The carrier includes a carrier frame including an associated array of carrier device areas. A lead frame panel may be positioned over the carrier such that the solder bumps on the active surfaces of the dice are adjacent and in contact with the associated leads of the associated device areas.Type: ApplicationFiled: March 26, 2007Publication date: October 2, 2008Inventors: Anindya Poddar, Jaime A. Bayan, Ashok S. Prabhu, Will K. Wong
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Patent number: 7227245Abstract: Broadly speaking, the invention pertains to substrates for use in semiconductor manufacturing. A peripheral ledge or similar structure can be provided in a die attach pad, so as to retain adhesive that may flow from the die support surface when the die is attached to the die attach pad. In this manner, adhesive is prevented from flowing off the die attach pad, where it can create unwanted conductive areas on the outer surface of an IC package. The accompanying reduction in area of the die support surface, and retention of adhesive from any downbond areas, also prevents delamination of the adhesive.Type: GrantFiled: February 26, 2004Date of Patent: June 5, 2007Assignee: National Semiconductor CorporationInventors: Jaime Bayan, Santhiran Nadarajah, Chan Peng Yee
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Patent number: 7186588Abstract: A method of fabricating a micro-array IC package is recited. A wafer has a B-stageable adhesive applied, and the wafer is diced. The individual dice are applied to a lead-frame via their adhesive, and wirebonded to associated leads. The lead-frame is then encapsulated, and solder connectors are applied. The lead-frame is then singulated to produce a plurality of lead-frame based micro-array packages. The process thus allows lead-frame based manufacturing methods to be employed in the production of BGA-type packages, allowing such packages to be produced faster and more efficiently.Type: GrantFiled: June 18, 2004Date of Patent: March 6, 2007Assignee: National Semiconductor CorporationInventors: Jaime A. Bayan, Santhiran S/O Nadarajah, Chan Chee Ling, Ashok S. Prabhu, Hasfiza Ramley, Chan Peng Yeen
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Patent number: 7181835Abstract: A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface of the porous block. A device for processing lead frames comprises a porous block with a first side and a second side, and a vacuum system connected to the first side of the porous block. The device may also include devices for attaching chips to the lead frame and wire bonding the chips to the lead frame.Type: GrantFiled: January 15, 2004Date of Patent: February 27, 2007Assignee: National Semiconductor CorporationInventors: Ah Lek Hu, Sharon Mei Wan Ko, Peng Yeen Chan, Jaime Bayan
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Patent number: 7102209Abstract: A lead-frame based substrate panel for use in semiconductor packaging is described. The substrate panel includes a lead-frame panel having at least one array of device areas. Each device area has a plurality of contacts. The lead-frame panel is filled with a dielectric material to form a relatively rigid substrate panel that can be used for packaging integrated circuits. The top surface of the dielectric material is typically substantially coplanar with the top surface of the lead-frame panel, and the bottom surface of the dielectric material is typically substantially coplanar with the bottom surface of the lead-frame panel.Type: GrantFiled: August 27, 2003Date of Patent: September 5, 2006Assignee: National Semiconductor CorporationInventors: Jaime Bayan, Ashok S. Prabhu, Fred Drummond
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Patent number: 7087986Abstract: A solder pad configuration for use in an IC package is described. Various embodiments of the invention describe IC packages, lead-frames, or substrate panels configured with generally noncircular solder pads at their bottom surfaces. The noncircular shapes allow for greater surface area than circular solder pads having diameters equal to a major dimension of the noncircular shapes, while maintaining the same metal-to-metal clearance between the pads and adjacent leads. This increased surface area provides for stronger and more reliable solder joints.Type: GrantFiled: June 18, 2004Date of Patent: August 8, 2006Assignee: National Semiconductor CorporationInventors: Jaime A. Bayan, Ashok S. Prabhu, Shaw Wei Lee
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Patent number: 7064419Abstract: A die attach region for use in an IC package is described. The die attach region employs a number of posts interconnected with a number of support risers to provide a structure that upholds a semiconductor die while facilitating flow of an encapsulant material underneath the die during encapsulation. The posts and risers can be arranged in a number of configurations that each facilitate flow of encapsulant material. This die attach region can be incorporated into a lead-frame structure or a substrate panel for ease and efficiency of manufacture.Type: GrantFiled: June 18, 2004Date of Patent: June 20, 2006Assignee: National Semiconductor CorporationInventors: Jaime A. Bayan, Ashok S. Prabhu, Chan Chee Ling, Lye Meng Kong, Santhiran S O Nadarajah
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Patent number: 7045035Abstract: A post singulation, die separation assembly for bulk separation of a plurality of dice in a singulated wafer from the adhesive backing of wafer saw tape. The die separation assembly includes a support base having a support surface. A feed tray includes a collection end positioned adjacent the base such that an elongated, substantially tin gap is formed between the tray collection end and at least a portion of the base. A flexible platform is movably supported atop the base support surface for movement along the base. Upon movement of the flexible platform down the down-ramped portion of the support base, a portion of the wafer saw tape thereat is peeled away from the respective die. The tape is the separated from the dice, releasing the respective dice onto the collection end of the feed tray in a manner substantially maintaining their forward alignment orientation of thereof.Type: GrantFiled: April 6, 2005Date of Patent: May 16, 2006Assignee: National Semiconductor CorporationInventors: Nikhil Kelkar, Ken Pham, Jaime A. Bayan, Cheol Hyun Han
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Patent number: 7023074Abstract: Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are provided with undercut regions that are left exposed during solder plating so that the solder plating also covers the exposed side and undercut segments of the contacts. When the resultant devices are soldered to an appropriate substrate (after singulation), each resulting solder joint includes a fillet that adheres very well to the undercut portion of contact. This provides a high quality solder joint that can be visually inspected from the side of the package.Type: GrantFiled: January 3, 2005Date of Patent: April 4, 2006Assignee: National Semiconductor CorporationInventors: Felix C. Li, Jaime A. Bayan, Santhiran Nadarajah, Ah Lek Hu
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Patent number: 6963124Abstract: A panel assembly of packaged integrated circuit devices including a conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.Type: GrantFiled: September 17, 2004Date of Patent: November 8, 2005Assignee: National Semiconductor CorporationInventors: Harry Kam Cheng Hong, Hu Ah Lek, Santhiran Nadarajah, Sharon Ko Mei Wan, Chan Peng Yeen, Jaime Bayan, Peter Howard Spalding
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Patent number: 6932136Abstract: A post singulation, die separation assembly for bulk separation of a plurality of dice in a singulated wafer from the adhesive backing of wafer saw tape. The die separation assembly includes a support base having a support surface, a first portion and an opposite second portion thereof. The second portion includes a down-ramped portion thereof skewed downwardly at a first acute angle from the support surface. A feed tray includes a collection end positioned adjacent the base second portion such that an elongated, substantially thin gap is formed between the tray collection end and at least a portion of the base second portion. A flexible platform is movably supported atop the base support surface for movement from the first portion to the second portion thereof. At the second portion, the platform passes downward through the gap formed between the tray collection end and the at least a portion of the base second portion.Type: GrantFiled: April 8, 2004Date of Patent: August 23, 2005Assignee: National Semiconductor CorporationInventors: Nikhil Kelkar, Ken Pham, Jaime A. Bayan, Cheol Hyun Han
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Patent number: 6933174Abstract: A leadless leadframe semiconductor package having a plurality of contacts, which have contact surfaces on the bottom surface of the package. At least some of the contacts have integrally formed stems that extend outward to the peripheral surface of the package. These stems have heights and widths less than the heights and widths of their corresponding contacts. A molded cap encapsulates at least a portion of the die, the stems and the contacts. Another aspect of the invention pertains to a leadless leadframe panel assembly having a conductive substrate panel that has at least one array of device areas, each array of device areas having a plurality of tie bars and a plurality of contacts. The contacts also have integrally formed stems that extend towards and connect to one of the tie bars. The stems have widths and heights that are less than the widths and heights of their corresponding contacts.Type: GrantFiled: September 30, 2004Date of Patent: August 23, 2005Assignee: National Semiconductor CorporationInventors: Harry Kam Cheng Hong, Hu Ah Lek, Santhiran Nadarajah, Sharon Ko Mei Wan, Chan Peng Yeen, Jaime Bayan, Peter Howard Spalding