Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.

Abstract: Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.

Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.

Abstract: Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.

Abstract: In one general aspect, an apparatus can include an input terminal, an output terminal and a ground terminal. The apparatus can also include an overcurrent protection device coupled between the input terminal and the output terminal. The apparatus can further include a thermal shunt device coupled between the output terminal and the ground terminal, the thermal shunt device being configured to, at a threshold temperature, operate in a thermally-induced low-impedance state.

Abstract: Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of the die, electrically and physically coupling the die to a packaging substrate, forming a sealant layer on the first surface of the die, forming an engagement structure within the trench, and infusing underfill between the sealant layer and the engagement structure and the packaging substrate.

Abstract: Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a side and forming a polymer layer on the side. The polymer layer has a central portion and a first frame portion spatially separated from the central portion to define a first channel. An underfill material may be provided to invade the channel and establish a mechanical joint between the polymer layer and the underfill material.

Abstract: The present invention provides for evaporation induced self-assembly (EISA) within microdroplets produced by a vibrating orifice aerosol generator (VOAG) for the production of monodisperse mesoporous silica particles. The process of the present invention exploits the concentration of evaporating droplets to induce the organization of various amphiphilic molecules, effectively partitioning a silica precursor to the hydrophilic regions of the structure. Promotion of silica condensation, followed by removal of the surfactant, provides ordered spherical mesoporous particles.

Abstract: Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of the die, electrically and physically coupling the die to a packaging substrate, forming a sealant layer on the first surface of the die, forming an engagement structure within the trench, and infusing underfill between the sealant layer and the engagement structure and the packaging substrate.

Abstract: Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a side and forming a polymer layer on the side. The polymer layer has a central portion and a first frame portion spatially separated from the central portion to define a first channel.

Abstract: Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner.

Abstract: Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner.